EP80579 Datasheet, PDF (1418/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.5.11.6.3 Checksum Word Calculation
The Checksum word (3Fh) is used to ensure that the base EEPROM image is a valid
image. The value of this word should be calculated by adding all the words (00h-3Fh),
including the Checksum word itself.
Note:
Hardware does not calculate the word 3Fh checksum during EEPROM write; it must be
calculated by software independently and included in the EEPROM write data. Hardware
does not compute a checksum over words 00h-3Fh during EEPROM reads in order to
determine validity of the EEPROM image; this field is provided strictly for SW
verification of EEPROM validity. All hardware configuration based on word 00h-3Fh
content is based on the validity of the Signature field of EEPROM Initialization Control
Word 1 (Signature must be 01b).
37.5.12
Error Handling
The overall principles and goals of error handling for the EP80579 are covered in
Chapter 5.0, “Error Handling”. This section covers the specifics of error handling
including bus errors and soft errors for this unit.
37.5.12.1 CSR (Target) Accesses
The following conditions must be met for a CSR access to be considered valid:
• Command must be CSR read or CSR write
• Length must be 0 (e.g.-4 bytes)
• Byte mask must be 0x0F, 0xF0, or 0x00
If the command violates any of the above conditions then the ICR.ERR_INTBUS
condition is asserted:
• All unsupported command types (i.e. those other than CSR read or CSR write) are
undefined operations and will result in indeterminate behavior by the GbE target.
• All single CSR writes are assumed to be 32-bit and will complete normally
regardless of the byte mask value. Writes using an unsupported byte mask will still
be flagged as an error as currently documented but will nonetheless be processed
as a 32-bit write
• Read and Write burst operations (length > 0) will be completed on the push/pull
buses as single operations. Reads will return 0xFFFF_FFFF for data and will assert
the push_data_err signal to the requestor. Write operations will discard the pull
data and the requested CSR or memory write will not be performed.
• If the data source of a CSR write operation asserts the internal_bus_data_error
signal, then the GbE target discards the data and the write operation is not
performed.
The generation of the ICR.ERR_INTBUS condition causes the INTBUS_ERR_STAT
register to be updated.
37.5.12.2 DMA Host (Master) Accesses
If the GbE is a master and receives a Push Data Error during a read transaction, then
an ICR.ERR_INTBUS condition is generated and the INTBUS_ERR_STAT register is
updated. All transactions are terminated.
This condition is considered fatal and further Host transaction requests from the GbE
unit are inhibited, until a soft reset is issued.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1418
August 2009
Order Number: 320066-003US