EP80579 Datasheet, PDF (1535/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.7.2
WUFC – Wake Up Filter Control Register (0x05808; RW)
This register is used to enable/disable each of the pre-defined and flexible filters
affecting wake up support. For most bits, a value of 1 means a wakeup for the specific
event is enabled, and a value of 0 means the wakeup is disabled. For example, when
MC=1, a packet containing an IA which matches the Directed Multicast Filter will
generate a wakeup event.
Table 37-132.WUFC - Wake Up Filter Control Register (0x05808; RW)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5808h
Offset End: 580Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5808h
Offset End: 580Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5808h
Offset End: 580Bh
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 20
19
18
17
16
15
14 : 08
07
06
05
04
03
02
01
00
RSVD
FLX3
FLX2
FLX1
FLX0
RSVD
RSVD
IPV6
IPV4
ARP
BC
MC
EX
MAG
Rsvd
Reserved. Should be set to 0.
Flexible Filter 3 Enable
Flexible Filter 2 Enable
Flexible Filter 1 Enable
Flexible Filter 0 Enable
Reserved. Should be set to 0.
Reserved. Should be set to 0.
Directed IPv6 Packet Wake Up Enable
Directed IPv4 Packet Wake Up Enable
ARP/IPv4 Request Packet Wake Up Enable
Broadcast Wake Up Enable
Directed Multicast Wake Up Enable
Directed Exact Wake Up Enable
Magic Packet Wake Up Enable
Reserved
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RW
RW
RW
RW
RW
RV
RW
RW
RW
RW
RW
RW
RW
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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