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EP80579 Datasheet, PDF (1638/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
Table 41-10. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 2 of
2)
Offset Start Offset End
Register ID - Description
Default
Value
00000018h 0000001Bh âOffset 0018h: TS_RSysTimeLo Registerâ on page 1647
0000h
0000001Ch 0000001Fh âOffset 001Ch: TS_RSysTimeHI Registerâ on page 1648
0000h
00000020h 00000023h âOffset 0020h: TS_SysTimeLo Registerâ on page 1649
0000h
00000024h 00000027h âOffset 0024h: TS_SysTimeHi Registerâ on page 1650
0000h
00000028h 0000002Bh âOffset 0028h: TS_TrgtLo Registerâ on page 1650
0000h
0000002Ch 0000002Fh âOffset 002Ch: TS_TrgtHi Registerâ on page 1651
0000h
00000030h 00000033h âOffset 0030h: TS_ASMSLo Registerâ on page 1652
0000h
00000034h 00000037h âOffset 0034h: TS_ASMSHi Registerâ on page 1653
0000h
00000038h 0000003Bh âOffset 0038h: TS_AMMSLo Registerâ on page 1654
0000h
0000003Ch 0000003Fh âOffset 003Ch: TS_AMMSHi Registerâ on page 1655
0000h
0040h at 20h
0043h at 20h
âOffset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel)â on page 1656
0000h
0044h at 20h
0047h at 20h
âOffset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event Register
Per Ethernet Channel)â on page 1658
0000h
0048h at 20h
004Bh at 20h
âOffset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per Ethernet
Channel)â on page 1659
0000h
004Ch at 20h
004Fh at 20h
âOffset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per Ethernet
Channel)â on page 1660
0000h
0050h at 20h
0053h at 20h
âOffset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per Ethernet
Channel)â on page 1661
0000h
0054h at 20h
0057h at 20h
âOffset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per Ethernet
Channel)â on page 1662
0000h
0058h at 20h
005Bh at 20h
âOffset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per Ethernet
Channel)â on page 1663
0000h
005Ch at 20h
005Fh at 20h
âOffset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register (Per
Ethernet Channel)â on page 1664
0000h
0140h at 10h
0143h at 10h
âOffset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel)â on page 1665
0000h
0144h at 10h
0147h at 10h
âOffset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per CAN
Channel)â on page 1666
0000h
0148h at 10h
014Bh at 10h
âOffset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per CAN
Channel)â on page 1667
0000h
000001F0h 000001F3h âOffset 01F0h: TS_Aux_TrgtLo Registerâ on page 1668
0000h
000001F4h 000001F7h âOffset 01F4h: TS_Aux_TrgtHi Registerâ on page 1668
0000h
00000200h 00000203h âOffset 0200h: L2 EtherType Registerâ on page 1669
000088F7h
0000204h
0000207h
âOffset 0204h: User Defined EtherType Registerâ on page 1669
00000000h
00000208h 0000020Bh âOffset 0208h:User Defined Header Offset Registerâ on page 1670
00000000h
0000020Ch 0000020Fh âOffset 020Ch:User Defined Header Registerâ on page 1670
00000000h
Intel® EP80579 Integrated Processor Product Line Datasheet
1638
August 2009
Order Number: 320066-003US
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