EP80579 Datasheet, PDF (332/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.8.2
Prioritized Arbitration Scheme
The high priority option in the arbitration scheme provides for a single “high priority”
channel to receive favorable latency and bandwidth service in the face of multiple
competing “normal priority” channels. This is accomplished by designating the high
priority channel using a priority enable bit and a two-bit field (to select one of four
channels) in the EDMA control register.
The internal EDMA controller arbiter modifies its arbitration algorithm to provide a
grant to the priority channel between the grants for each of the other channels, which
retain their round-robin prioritization relative to each other. For example, given a
hypothetical memory interface bandwidth of 4 GB/s, the priority-modified scheme
would result in 2 GB/s (half the available bandwidth) for the designated priority
channel, and the remaining 2 GB/s split equally among the other competing channels.
The limitation that a single channel at a time be designated as the priority channel is an
acknowledgement that quality of service differences, given multiple “priority” channels,
would be slight in this implementation with two-level arbitration and only four
competing channels. It is anticipated that software will be able to determine when an
application is particularly sensitive to service level, has been allocated a channel, and
will manage the assignment of priority accordingly. If more than one such “sensitive”
application is in flight at the same time, it is perceived to be more efficacious to allow
fair competition between those sources, and let the kernel or device driver software
attempt to manage competition for resources at the system level to prevent service
level problems.
Each EDMA channel supports dynamic modification to the priority channel settings
(while one or more channels are active). A write to the control register that changes
the priority channel configuration takes affect at the next arbitration decision point
after the write has completed. There is no direct interlock between the arbiter
configuration and any of the active channels. Such an event is effectively an
environment change, orthogonal to work in progress on any given channel.
12.9
Configuration
The EDMA controller uses memory-mapped configuration registers for the majority of
its per channel register sets. The controller is software compatible with standard PCI
device configuration and implements a standard PCI header in its configuration-
mapped register set as shown in Figure 12-1. The memory-mapped register space
associated with the controller is identified by a 32-bit memory Base Address Register
(BAR). Table 12-1 provides an overview of the memory-mapped register set for a
representative channel of the controller.
Table 12-1. Channel 0 Memory-mapped Register Set
Memory Mapped I/O for EDMA Channel 0
Channel Control Register (CCR0)
Channel Status Register (CSR0)
Current Descriptor Addr Reg (CDAR0)
Current Descriptor Upper Addr Reg (CDUAR0)
Source Address Register (SAR0)
Source Upper Address Register (SUAR0)
Destination Address Register (DAR0)
Destination Upper Address Register (DUAR0)
Memor
y
offset
00-3h
04-07h
08-0Bh
0C-0Fh
10-13h
14-17h
18-1Bh
1C-1Fh
Access
RW
RWC,
RO
RO
RO
RO
RO
RO
RO
Size
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
Default
Sticky
0000_0000h
No
0000_0000h
No
0000_0000h
No
0000_0000h No
0000_0000h
No
0000_0000h
No
0000_0000h
No
0000_0000h
No
Intel^® EP80579 Integrated Processor Product Line Datasheet
332
August 2009
Order Number: 320066-003US