EP80579 Datasheet, PDF (970/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.7
Data Encoding and Bit Stuffing
The CMI USB employs NRZI data encoding (Non-Return to Zero Inverted) when
transmitting packets. Full details on this implementation are given in the USB
Specification, Rev. 2.0.
The USB employs NRZI data encoding when transmitting packets. In NRZI encoding, a
1 is represented by no change in level and a 0 is represented by a change in level. A
string of zeros causes the NRZI data to toggle each bit time. A string of ones causes
long periods with no transitions in the data. In order to ensure adequate signal
transitions, bit stuffing is employed by the transmitting device when sending a packet
on the USB. A 0 is inserted after every six consecutive 1s in the data stream before the
data is NRZI encoded to force a transition in the NRZI data stream. This gives the
receiver logic a data transition at least once every seven bit times to guarantee the
data and clock lock. A waveform of the data encoding is shown in Figure 25-2.
Figure 25-2. USB Data Encoding
CLOCK
Data
Bit Stuffed Data
NRZI Data
25.8
25.8.1
25.8.2
25.8.3
Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire
transmission. The data “one” that ends the Sync Pattern is counted as the first one in a
sequence. Bit stuffing is always enforced, without exception. If required by the bit
stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of-
packet (EOP) signal.
Bus Protocol
Bit Ordering
Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSB, the
most significant bit (MSb) last.
SYNC Field
All packets begin with a synchronization (SYNC) field, which is a coded sequence that
generates a maximum edge transition density. The SYNC field appears on the bus as
IDLE followed by the binary string “KJKJKJKK,” in its NRZI encoding. It is used by the
input circuitry to align incoming data with the local clock and is defined to be eight bits
in length. SYNC serves only as a synchronization mechanism and is not shown in the
following packet diagrams in Section 25.8.3. The last two bits in the SYNC field are a
marker that is used to identify the first bit of the PID. All subsequent bits in the packet
must be indexed from this point.
Packet Field Formats
All packets have distinct start and end of packet delimiters. Full details are given in the
USB Specification.
Intel^® EP80579 Integrated Processor Product Line Datasheet
970
August 2009
Order Number: 320066-003US