EP80579 Datasheet, PDF (944/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-4. PCISTS - Device Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0280h
Power Well: Core
Bit Range
10 : 09
08
07
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
DEVT
Reserved
Reserved
Reserved
Reserved
Reserved
INTSTAT
Reserved
DEVSEL# Timing Status: This 2-bit field defines the
timing for DEVSEL# assertion. These read-only bits
indicate the DEVSEL# timing when performing a positive
decode. Since USB is not PCI-based, the value in this field
is arbitrary.
Hardwired as‘0’.
Hardwired as‘1’
Hardwired as‘0’.
Hardwired as‘0’.
Hardwired as‘0’.
Interrupt Status: This read-only bit reflects the state of
this function’s interrupt at the input of the enable/disable
logic.
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
The value reported in this bit is independent of the value in
the Interrupt Enable bit.
Reserved
Bit Reset
Value
01h
0h
1
0h
0h
0h
0h
000h
Bit Access
RO
RO
25.1.1.4
RID - Revision ID Register
The value reported in this register depends on the value written to the Revision ID in
Device 31, Function 0, Offset 08h.
Table 25-5. RID - Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
REVID
Revision ID: 8-bit value that indicates the revision
number of the USB1.1 interface.The value reported in this
register depends on the value written to the Revision ID in
Device 31, Function 0, Offset 08h. This register follows the
ICH revision ID scheme as defined in Section 19.2.1.4,
“Offset 08h: RID - Revision ID Register” on page 736.
Bit Reset
Value
Variable
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
944
August 2009
Order Number: 320066-003US