EP80579 Datasheet, PDF (1913/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
50.2.1
Note:
50.2.1.1
Catastrophic Thermal Protection
The EP80579 provides catastrophic thermal protection via an on-die thermal sensor
that detects when the silicon has reached approximately 20°C above T_CASE-MAX. This
catastrophic trip point is programmed at the factory. The catastrophic trip point will
initiate the Processor Thermal Trip control sequence, which is described in Section
50.2.1.1, “THRMTRIP# Control Sequence”. Once the thermal sensor has detected this
over heat condition, THRMTRIP# is asserted.
THRMTRIP# is also available as an input pin to support platform thermal management
requirements. An external thermal sensor could be implemented to monitor the
platform thermal condition, asserting THRMTRIP# when catastrophic thermal
conditions exist on the platform. The EP80579 receives this signal and initiates the
THRMTRIP# Control Sequence described in Section 50.2.1.1, “THRMTRIP# Control
Sequence”.
Intel recommends that an external thermal sensor be used to protect the EP80579 and
the system against excessive temperature. Even with the activation of THRMTRIP#,
which halts all internal clocks and activity, leakage current can be high enough such
that the EP80579 cannot be protected in all conditions without completely removing the
supplied power source. If the external thermal sensor detects the silicon has reached a
catastrophic temperature approximately 20°C above TCASE-MAX, or if the THRMTRIP#
signal is asserted, the VCC supply to the processor must be turned off within 500 ms to
prevent silicon damage due to thermal runaway.
THRMTRIP# Control Sequence
A catastrophic thermal trip event will assert THRMTRIP#, which indicates that the on-
die thermal sensor has detected an overheat condition. Intel recommends that
immediate action be taken to prevent silicon damage.
The temperature which the EP80579 activates this thermal control sequence is not user
configurable and is not software visible. The following list provides additional
information:
• If THRMTRIP# goes active, the processor is indicating an overheat condition, and
will immediately transition to an S5 state. However, since the processor has
overheated, it will not respond to the STPCLK# pin with a stop grant special cycle.
Therefore, the EP80579 will not wait for one.
• Immediately upon seeing THRMTRIP# low, EP80579 will initiate a transition to the
S5 state, drive signals SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit. The
transition will generally look like a power button override.
• When a THRMTRIP# event occurs, the EP80579 must power down immediately
without following the normal S0 -> S5 path. This can happen in parallel, but the
EP80579 must immediately enter a power down state. The EP80579 will do this by
driving signals SLP_S3#, SLP_S4#, and SLP_S5# within 3 PCICLKs after sampling
THRMTRIP# active.
• If the processor is running extremely hot and is heating up, it is possible (although
very unlikely) that components around it are no longer executing cycles properly.
Therefore, if THRMTRIP# goes active, any other components that are relying on
state machine logic to perform the power down, may not power down correctly.
Because the state machine may not be working, the system may not power down
completely.
The EP80579 will follow the flow in the steps that follow for THRMTRIP#:
1. At boot (PLTRST# low), THRMTRIP# ignored.
2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#,
SLP_S4#, and SLP_S5# fire, and normal sequence of sleep machine starts.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1913