EP80579 Datasheet, PDF (826/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-15. Offset 20h: LBAR – Legacy Bus Master Base Address Register when SCC is
SATA with AHCI PI
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 20h
Offset End: 23h
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 16
15 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
BA
Reserved
RTE
Reserved
Base Address (BA): Base address of the I/O space.
• Note on bit 4: When CC.SCC is 01h, bit 4 is RW,
resulting in requesting 16B of I/O space. When CC.SCC is
not 01h, this bit is RO and reports 0, resulting in
requesting 32B of I/O space.
• Bits 15:5 are always RW with default value of 0.
•
Reserved
Resource Type Indicator (RTE): Indicates a request for
I/O space.
Bit Reset
Value
0h
0h
0h
1h
Bit Access
RO
RW
RO
RO
23.1.1.13 Offset 24h: ABAR – AHCI Base Address Register
This register allocates space for the memory registers defined in section 1.3.
Note that hardware only supports non-combined mode.
Note that this register must be programmed to value of 0001_0000h or greater,
otherwise memory cycles targeting the ABAR range may not accepted.
Table 23-16. Offset 24h: ABAR – AHCI Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 24h
Offset End: 27h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 10
09 : 04
03
02 : 01
00
Bit Acronym
Bit Description
Sticky
BA
Reserved
PF
TP
RTE
Base Address (BA): Base address of register memory
space (aligned to 1 KB)
Reserved
Prefetchable (PF): Indicates that this range is not pre-
fetchable
Type (TP): Indicates that this range can be mapped
anywhere in 32-bit address space
Resource Type Indicator (RTE): Indicates a request for
register memory space.
Bit Reset
Value
0h
0h
0h
00h
0h
Bit Access
RW
RO
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
826
August 2009
Order Number: 320066-003US