EP80579 Datasheet, PDF (912/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1.3
Offset 03h: HCMD: Host Command Register
This eight bit field is transmitted by the host controller in the command field of the SMB
protocol during the execution of any command.
Table 24-21. Offset 03h: HCMD: Host Command Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 03h
Offset End: 03h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
HST_CMD
This 8-bit field is transmitted by the host controller in
the command field of the SMBus protocol during the
execution of any command.
Sticky
Bit Reset
Value
00h
Bit Access
RW
24.3.1.4
Offset 04h: TSA: Transmit Slave Address Register
This register is transmitted by the host controller in the slave address field of the SMB
protocol. This is the address of the target.
Table 24-22. Offset 04h: TSA: Transmit Slave Address Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 04h
Offset End: 04h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 01
00
Bit Acronym
Bit Description
ADDRESS
RW
7-bit address of the targeted slave
Direction of the host transfer.
0 = write
1 = read
Sticky
Bit Reset
Value
0000000h
Bit Access
RW
0h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
912
August 2009
Order Number: 320066-003US