EP80579 Datasheet, PDF (1372/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 37-22.TCP/IP Context Transmit Descriptor Command Field (TDESC.TUCMD)
Rsvd: Reserved
DEXT: Descriptor Extension (Must be 1 for this descriptor type)
Rsvd: Reserved
RS: Report Status
TSE: TCP Segmentation Enable
IP: IP Packet Type (IPv4=1, IPv6=0)
TCP: Packet Type (TCP=1,UDP=0)
The TCP bit identifies the packet as either TCP or UDP (non-TCP). This effects the
processing of the header information. The IP bit is used to indicate what type of IP
packet is used in the segmentation process. This is necessary for the EP80579’s GbE to
know where the IP Payload Length field is located. This does not override the checksum
insertion bit, TDESC.POPTS IXSM bit. The IP bit must only be set for IPv4 packets and
cleared for IPv6 packets.
The TCP Segmentation feature also provides access to a generic block send function
and may be useful for performing “segmentation offload” in which the header
information is constant. By clearing both the TCP and IP bits, a block of data may be
broken down into frames of a given size, a constant, arbitrary length header may be
prepended to each frame, and two checksums optionally added.
TSE indicates that this descriptor is setting the TCP segmentation context. If this bit is
not set, the checksum off loading context for normal (non-“TCP Segmentation”)
packets is written. When a descriptor of this type is processed, the device will
immediately update the context in question (TCP Segmentation or checksum off
loading) with values from the descriptor. This means that if any normal packets or TCP
Segmentation packet are in progress (a descriptor with EOP set has not been received
for the given context) the results will likely be undesirable.
RS tells the hardware to report the status information for this descriptor. Because this
descriptor does not transmit data, only the DD bit in the status word will be valid. Refer
to Figure 37-23 for the layout of the status field.
Figure 37-23.TCP/IP Context Transmit Descriptor Status (TDESC.TUSTATUS)
3
2
1
0
Rsvd
DD
Rsvd: Reserved
DD: Descriptor Done
The reserved bits are reserved values and are ignored, but if written should be set to 0
for future compatibility.
The DEXT bit identifies this descriptor as one of the extended descriptor types and
must be set to 1.
IDE activates the transmit interrupt delay timer. Hardware loads a countdown register
when it writes back a transmit descriptor that has the RS bit and the IDE bit set. The
value loaded comes from the Transmit Interrupt Delay Value Register (TIDV.IDV). When
the count reaches 0, a transmit interrupt occurs. Hardware always loads the transmit
interrupt counter whenever it processes a descriptor with IDE set even if it is already
Intel^® EP80579 Integrated Processor Product Line Datasheet
1372
August 2009
Order Number: 320066-003US