EP80579 Datasheet, PDF (988/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.17 Offset 51h: PM_NEXT - Next Item Pointer #1 Register
Table 26-19. Offset 51h: PM_NEXT - Next Item Pointer #1 Register
Description: Lockable:Not D3-to-DO
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 51h
Offset End: 51h
Size: 8 bit
Default: 58h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
PM_NEXT
This register defaults to 58h, which indicates that the next
capability registers begin at configuration offset 58h. This
register is writable when the WRT_RDONLY bit is set. This
allows BIOS to effectively hide the Debug Port capability
registers, if necessary. This register must only be written
during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only
values of 58h (Debug Port visible) and 00h (Debug Port
invisible) are expected to be programmed in this register.
Bit Reset
Value
58h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
988
August 2009
Order Number: 320066-003US