EP80579 Datasheet, PDF (820/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-3. Offset 04h: CMD - Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
MWIE
SCE
BME
MSE
IOSE
Memory Write and Invalidate Enable (MWIE): Reserved
Special Cycle Enable (SCE): Reserved
Bus Master Enable (BME): Controls the SATA
Controller’s ability to act as a master for data transfers.
This bit does not impact the generation of completions for
split transaction commands.
Memory Space Enable (MSE): Controls access to the
SATA Controller’s target memory space (for AHCI).’
I/O Space Enable (IOSE): Controls access to the SATA
Controller’s target I/O space.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RO
RW
RW
RW
23.1.1.3 Offset 06h: STS - Device Status Register
Table 23-4. Offset 06h: STS - Device Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 02B0h
Power Well: Core
Bit Range
15
14
13
12
11
10 : 09
08
07
06
05
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMA
RTA
STA
DEVT
DPD
Reserved
Reserved
C66
Detected Parity Error (DPE): Set when the SATA
Controller detects a parity error on its interface.
Signaled System Error (SSE): The SATA Controller will
never generate an SERR#.
Received Master-Abort Status (RMA): Set when the
SATA Controller receives a master abort to a cycle it
generated.
Received Target-Abort Status (RTA): Set when the
SATA Controller receives a target abort to a cycle it
generated.
Signaled Target-Abort Status (STA): Reserved. The
SATA Controller will never generate a target abort.
DEVSEL# Timing Status (DEVT): Controls the device
select time for the SATA Controller’s PCI interface.
Master Data Parity Error Detected (DPD): Set when
the SATA Controller, as a master, either detects a parity
error or sees the parity error line asserted, and the parity
error response bit (bit 6 of the command register) is set.
This bit can only be set on read completions received from
the backbone where there is a parity error.
Fast Back-to-Back Capable: Reserved
Reserved
66 MHz Capable
Bit Reset
Value
0h
0h
0h
0h
0h
01h
0h
1h
0h
1h
Bit Access
RWC
RO
RWC
RWC
RO
RO
RWC
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
820
August 2009
Order Number: 320066-003US