EP80579 Datasheet, PDF (616/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.12 Offset A8h: DRRTC01 - Receive Enable Reference Output Timing
Control Register
This register determines DQS 7, 6, 5, & 4 input buffer enable timing delay.
Table 16-238.Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control
Register
Description: DRRTC01: Receive Enable Reference Output Timing Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: A8h
Offset End: ABh
Size: 32 bit
Default: 06060606h
Power Well: Core
Bit Range
31 :24
23 :16
15 :08
7 :00
Bit Acronym
Bit Description
RCVEN07
RCVEN06
RCVEN05
RCVEN04
Receiver enable delay for DQS7
Receiver enable delay for DQS6
Receiver enable delay for DQS5
Receiver enable delay for DQS4
Sticky
Y
Y
Y
Y
Bit Reset
Value
06h
06h
06h
06h
Bit Access
RW
RW
RW
RW
16.5.1.13 Offset C4h: DRRTC02 - Receive Enable Reference Output Timing
Control Register
This register determines DQS 8 input buffer enable timing delay.
Table 16-239.Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control
Register
Description: DRRTC02: Receive Enable Reference Output Timing Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: C4h
Offset End: C4h
Size: 8 bit
Default: 06h
Power Well: Core
Bit Range
7 :00
Bit Acronym
Bit Description
RCVEN08 Receiver enable delay for DQS8
Sticky
Y
Bit Reset
Value
06h
Bit Access
RW
16.5.1.14 DQS Calibration Registers
The DQSOFCS is a group of six registers that control the fine delay used to center DQS
edges to the DQ data eye during read operations. There is a delay entry for each nibble
of the DDR data bus for each rank. The coarse delay is controlled by the DRAMDLLC
register. The equations for the fine and coarse delays are shown below. Note that
“Delay Element” and “Delay_Uncomp” are defined in the DRRTC register section. Also
note that there is a separate coarse delay control for each “chunk” of the DDR I/O
cluster as defined in the DRAMDLLC register section.
Note: these registers may have to be saved and restored on S3
Intel^® EP80579 Integrated Processor Product Line Datasheet
616
August 2009
Order Number: 320066-003US