EP80579 Datasheet, PDF (647/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-293.Offset 284h: WL_CNTL[4:0] - Write Levelization Control Register
Description: WL_CNTL[4:0]: Write Levelization Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 284h at 4h
Offset End: 294h at 4h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :16
15 :14
13 :12
11 :8
7 :2
1 :1
0 :0
Bit Acronym
Bit Description
Sticky
Reserved Reserved
N
Reserved Reserved
N
Reserved Reserved
N
Delay Select
WL_CNTRL
Y
See Table 16-294
WDLL_CNTL
Length controls for Slave Write DLL (WDLL). A delay of 0
up to 3/8 of clk1x can be programmed using this CSR.
Y
Control bit for Clock gating of DQ/DQS.
WDLL_CLKG
0– Disable clock gating for DQ/DQS
1– Enable clock gating for DQ/DQS
Y
Note: for WL_CNTL[4], WDLL_CLKG must be equal to 0
Bypass Write DLL. This bit is used only for centering DQS
to the DQ eye. For write leveling, see Table 16-294.
0 – Bypass DLL
BYP_WDLL 1 – Output with WDLL
Y
Before enabling/setting this bit to 1, software needs to first
program the appropriate values in DRAMDLLC.SLVLEN &
WL_CNTL[x].WDLL_CNTL.
Bit Reset
Value
0000h
00b
00b
0000b
00000b
0b
0b
Bit Access
RO
RW
RO
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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