EP80579 Datasheet, PDF (542/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.23 Offset 34h: CAPPTR - Capabilities Pointer Register
The CAPPTR provides the offset that is the pointer to the location where the first set of
capabilities registers is located.
Table 16-162.Offset 34h: CAPPTR - Capabilities Pointer Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 34h
Offset End: 34h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: 50h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
CAP_PTR
Capabilities Pointer: Pointer to first PCI Express*
Capabilities Structure register block, which is the first of
the chain of capabilities.
Sticky
Bit Reset
Value
50h
Bit Access
RO
16.4.1.24 Offset 3Ch: INTRLINE - Interrupt Line Register
Table 16-163.Offset 3Ch: INTRLINE - Interrupt Line Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 3Ch
Offset End: 3Ch
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
INTRC
Interrupt Connection: BIOS writes the interrupt routing
information to this register to indicate which input of the
interrupt controller that connects this device.
Bit Reset
Value
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
542
August 2009
Order Number: 320066-003US