EP80579 Datasheet, PDF (1685/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
42.4.1.7.5 Synchronous Intel 8-word Read Access
Figure 42-10.Intel Synchronous 8-word Read
EX_CLK
EX _CS_N
EX_ADDR
EX_ALE
EX_RD_N
EX_WR_N
EX_BE_N
EX_IOWAIT _N
EX _DATA
EX_PARITY
STATE
Intel Synchronous 8-Word Read
-0 -
-1 -
-2-
-3 -
-4-
-5 -
-8-
-9 -
- 10 -
ADDR0
IDLE
ADDRESS
WAIT
DATA0_HI
DATA 0_ LO
PAR0_HI
PAR 0_HI
WAIT
DATA0
DATA1
DATA7_HI
DATA 7_ LO
PAR7 _HI
PAR7_LO
DATA 6
DATA7
IDLE
The above timing diagram shows an 8-word read to a Synchronous Intel device such as
Synchronous Intel StrataFlash. Depending on the EX_CLK period, the latency count bits
in the Intel Synchronous Device read configuration register needs to be programmed
appropriately based on the timing parameters for the specific device. The Expansion
bus controller will always wait in cycles 1 and 2, regardless of EX_IOWAIT_N. The
device will then assert EX_IOWAIT_N for several cycles and deassert EX_IOWAIT_N
when its ready to transfer data. After the device deasserts EX_IOWAIT_N, it will
transfer the remaining words until all 8 words are transferred. The Expansion bus
controller and Synchronous Intel device both support wrapping for 8-word reads,
therefore ADDR0 is not always aligned to an 8-word boundary. The STATE signal shows
the internal Expansion bus state.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1685