EP80579 Datasheet, PDF (450/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.8
Offset 0Dh: MLT - Master Latency Timer Register
Device 0 in the IMCH is not a PCI master so this register is not implemented.
Table 16-62. Offset 0Dh: MLT - Master Latency Timer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 0Dh
Offset End: 0Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
07 : 00
Reserved Reserved
Bit Description
Sticky
Bit Reset
Value
00h
Bit Access
16.2.1.9 Offset 0Eh: HDR - Header Type Register
Table 16-63. Offset 0Eh: HDR - Header Type Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 0Eh
Offset End: 0Eh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
HDR
PCI Header: This value indicates the Header Type for the
IMCH Device 0.
00h = IMCH is a multi-function device with a standard
header layout.
Bit Reset
Value
00h
Bit Access
RO
16.2.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register
This value is used to identify the vendor of the subsystem.
Table 16-64. Offset 2Ch: SVID - Subsystem Vendor Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 2Ch
Offset End: 2Dh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SUBVID
Subsystem Vendor ID: This field must be programmed
during boot-up to indicate the vendor of the system board.
Bit Reset
Value
0000h
Bit Access
RWO
Intel^® EP80579 Integrated Processor Product Line Datasheet
450
August 2009
Order Number: 320066-003US