EP80579 Datasheet, PDF (31/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
30.2.2.3 MICW3 - Master Initialization Command Word 3 Register ....................1121
30.2.2.4 SICW3 - Slave Initialization Command Word 3 Register ......................1121
30.2.2.5 ICW4[0-1] - Initialization Command Word 4 Register..........................1122
30.2.2.6 OCW1[0-1] - Operational Control Word 1 (Interrupt Mask)
Register .......................................................................................1122
30.2.2.7 OCW2[0-1] - Operational Control Word 2 Register..............................1123
30.2.2.8 OCW3[0-1] - Operational Control Word 3 Register..............................1124
30.2.2.9 ELCR1 - Master Edge/Level Control Register ......................................1125
30.2.2.10 ELCR2 - Slave Edge/Level Control Register ........................................1126
30.2.3 Interrupt Handling.................................................................................1127
30.2.3.1 Generating Interrupts.....................................................................1127
30.2.3.2 Acknowledging Interrupts ...............................................................1127
30.2.3.3 Hardware/Software Interrupt Sequence ............................................1127
30.2.4 Initialization Command Words (ICW) .......................................................1128
30.2.4.1 ICW1 ...........................................................................................1128
30.2.4.2 ICW2 ...........................................................................................1128
30.2.4.3 ICW3 ...........................................................................................1128
30.2.4.4 ICW4 ...........................................................................................1129
30.2.5 Operation Command Words (OCW)..........................................................1129
30.2.6 Modes of Operation ...............................................................................1129
30.2.6.1 Fully Nested Mode..........................................................................1129
30.2.6.2 Special Fully Nested Mode...............................................................1129
30.2.6.3 Automatic Rotation Mode (Equal Priority Devices)...............................1130
30.2.6.4 Specific Rotation Mode (Specific Priority)...........................................1130
30.2.6.5 Poll Mode......................................................................................1130
30.2.6.6 Edge and Level Triggered Mode .......................................................1130
30.2.7 End of Interrupt (EOI) operations ............................................................1131
30.2.7.1 Normal EOI ...................................................................................1131
30.2.7.2 Automatic EOI Mode.......................................................................1131
30.2.8 Masking Interrupts ................................................................................1131
30.2.8.1 Masking on an Individual Interrupt Request.......................................1131
30.2.8.2 Special Mask Mode.........................................................................1131
30.2.9 Steering of PCI Interrupts ......................................................................1131
30.3 Advanced Interrupt Controller: APIC .................................................................1132
30.3.1 Interrupt Handling.................................................................................1132
30.3.2 PCI/PCI Express* Message-Based Interrupts.............................................1132
30.3.2.1 Front Side Bus Interrupt Delivery .....................................................1133
30.3.2.2 Edge-Triggered Operation ...............................................................1133
30.3.2.3 Level-Triggered Operation...............................................................1133
30.3.2.4 Registers Associated with Front-Side Bus Interrupt Delivery ................1133
30.3.2.5 EOI..............................................................................................1133
30.3.2.6 Interrupt Message Format ..............................................................1133
30.3.3 APIC Memory-Mapped Register Details .....................................................1135
30.3.3.1 APIC_IDX - Index Register ..............................................................1135
30.3.3.2 APIC_DAT – Data Register .............................................................1136
30.3.3.3 APIC_EOI - EOI Register .................................................................1136
30.3.4 Index Registers.....................................................................................1137
30.3.4.1 APIC_ID – Identification Register .....................................................1138
30.3.4.2 APIC_VS - Version Register .............................................................1138
30.3.4.3 APIC_RTE[0-39] - Redirection Table Entry.........................................1139
30.4 PCI Interrupts via /PCI Express* ......................................................................1142
30.5 Serial Interrupt ..............................................................................................1142
30.5.1 Overview .............................................................................................1142
30.5.2 Start Frame..........................................................................................1142
30.5.3 Data Frames.........................................................................................1143
30.5.4 Stop Frame ..........................................................................................1143
30.5.5 Serial Interrupts Not Supported via SERIRQ..............................................1143
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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