EP80579 Datasheet, PDF (749/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.4.2 Offset 82h: IOE: I/O Enables Register
Table 19-24. Offset 82h: IOE: I/O Enables Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 82h
Offset End: 83h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :14
13
12
11
10
09
08
07 :04
03
Bit Acronym
Bit Description
Sticky
Reserved
ME2
SE
ME1
KE
HGE
LGE
Reserved
FDE
Reserved
Micro controller Enable 2:
0 = Disable
1 = Enables the decoding of the I/O locations 4Eh and 4Fh
to the LPC interface. This range is used for a
microcontroller.
Super I/O Enable:
0 = Disable
1 = Enables the decoding of the I/O locations 2Eh and 2Fh
to the LPC interface. This range is used for Super I/O
devices.
Micro controller Enable 1:
0 = Disable
1 = Enables the decoding of the I/O locations 62h and 66h
to the LPC interface. This range is used for a
microcontroller.
Keyboard Enable:
0 = Disable
1 = Enables the decoding of the I/O locations 60h and 64h
to the LPC interface. This range is used for a
microcontroller.
High Gameport Enable:
0 = Disable
1 = Enables decoding of the I/O locations 208h to 20Fh to
LPC
Low Gameport Enable:
0 = Disable
1 = Enables decoding of the I/O locations 200h to 207h to
LPC
Reserved
Floppy Drive Enable:
0 = Disable
1 = Enables decoding of the FDD range to LPC. Range is
selected by LIOD.FDE Decode Range Register (D31, F0,
80h, bit 12)
Bit Reset
Value
00h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
749