EP80579 Datasheet, PDF (1507/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.4
Note:
MPC – Missed Packet Count Register
This register counts the number of missed packets. Packets are missed when the
receive FIFO has insufficient space to store the incoming packet. This could be caused
because of too few buffers allocated, or because there is insufficient bandwidth on the
internal bus. Events setting this counter cause the receiver overrun interrupt condition
(ICR.RXO) to be set. This register does not count packets dropped due to the receiver
being disabled.
Missed packets will be included/counted in the “TPR – Total Packets Received Register”
on page 1528 as well as in the Total Octets Received counter of the “TORL – Total
Octets Received Low Register” on page 1525 and the “TORH – Total Octets Received
High Register” on page 1526.
Table 37-82. MPC: Missed Packet Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4010h
Offset End: 4013h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4010h
Offset End: 4013h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4010h
Offset End: 4013h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
MPC
Missed Packets Count
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.5
SCC – Single Collision Count Register
This register counts the number of times that a successfully transmitted packet
encountered a single collision. This register will only increment if transmits are enabled
and the device is in half-duplex mode.
Table 37-83. SCC: Single Collision Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4014h
Offset End: 4017h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4014h
Offset End: 4017h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4014h
Offset End: 4017h
Size: 32 bits
Default: 0000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
SCC
Number of times a transmit encountered a single collision.
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1507