EP80579 Datasheet, PDF (1166/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.3.4
32.3.5
32.3.6
get completely serviced before the next timer match occurs. Interrupts may get lost
and/or system performance may be degraded in this case.
Each timer is NOT required to support the periodic mode of operation. A capabilities bit
indicates if the particular timer supports periodic mode. The reason for this is that
supporting the periodic mode adds a significant number of gates.
For CMI, only Timer 0 supports periodic mode. The following usage model is expected:
1. Software clears the ENABLE_CNF bit to prevent any interrupts.
2. Software clears the main counter by writing a value of 00h to it.
3. Software sets the TIMER0_VAL_SET_CNF bit.
4. Software writes the new value in the TIMER0_COMPARATOR_VAL register.
5. Software sets the ENABLE_CNF bit to enable interrupts.
The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-
bit write in a 32-bit environment except if only the periodic rate is being changed
during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then
the following software solution will always work regardless of the environment:
1. Set TIMER0_VAL_SET_CNF bit
2. Set the lower 32 bits of the Timer0 Comparator Value register
3. Set TIMER0_VAL_SET_CNF bit
4. Set the upper 32 bits of the Timer0 Comparator Value register
Enabling the Timers
The BIOS or operating system PnP code must rout the interrupts. This includes the
Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge
or level type for each timer).
The Device Driver code must do the following for an available timer:
1. Set the Overall Enable bit (Offset 04h, bit 0).
2. Set the timer type field (selects one-shot or periodic).
3. Set the interrupt enable.
4. Set the comparator value.
Interrupt Levels
Interrupts directed to the 8259s are active high. See Chapter 30.0, “Interrupts,” for
information regarding the polarity programming of the I/O APIC for detecting internal
interrupts.
If the interrupts are mapped to the I/O APIC and set for level-triggered mode, they can
be shared with PCI interrupts. If more than one timer is configured to share the same
IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the
timers to level-triggered mode. Edge-triggered interrupts cannot be shared.
Handling Interrupts
If each timer has a unique interrupt and the timer has been configured for edge-
triggered mode, then there are no specific steps required. No read is required to
process the interrupt.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1166
August 2009
Order Number: 320066-003US