EP80579 Datasheet, PDF (1616/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
40.4.3.5
40.4.3.6
40.4.3.7
40.4.3.8
40.4.3.9
40.4.4
40.4.4.1
Note:
Transmit FIFO Service Request Flag (TFS) (Read-Only,
Maskable Interrupt)
The Transmit FIFO service request flag (TFS) is a read-only bit that is set when the
transmit FIFO is nearly empty and requires service to prevent an underrun. TFS is set
any time the transmit FIFO has the same or fewer entries of valid data than indicated
by the Transmit FIFO Threshold and it is cleared when it has more entries of valid data
than the threshold value. When the TFS bit is set, an interrupt request is made unless
the transmit FIFO interrupt request enable (TIE) bit is cleared. After the CPU fills the
FIFO such that it exceeds the threshold, the TFS flag (and the service request and/or
interrupt) is automatically cleared.
Receive FIFO Service Request Flag (RFS) (Read-Only,
Maskable Interrupt)
The receive FIFO service request flag (RFS) is a read-only bit that is set when the
receive FIFO is nearly filled and requires service to prevent an overrun. RFS is set any
time the receive FIFO has the same or more entries of valid data than indicated by the
Receive FIFO Threshold and it is cleared when it has fewer entries than the threshold
value. When the RFS bit is set, an interrupt request is made unless the receive FIFO
interrupt request enable (RIE) bit is cleared. After the CPU reads the FIFO such that it
has fewer entries than the RFT value, the RFS flag (and the service request and/or
interrupt) is automatically cleared.
Receiver Overrun Status (ROR) (Read/Write, Non-Maskable
Interrupt)
The receiver overrun status bit (ROR) is a read/write bit that is set when the receive
logic attempts to place data into the receive FIFO after it has been completely filled.
Each time a new piece of data is received, the set signal to the ROR bit is asserted and
the newly received data is discarded. This process is repeated for each new piece of
data received until at least one empty FIFO entry exists. When the ROR bit is set, an
interrupt request is made. Writing 1 to this bit resets ROR status and its interrupt
request.
Transmit FIFO Level
This 4-bit value shows how many valid entries are currently in the Transmit FIFO.
Receive FIFO Level
This 4-bit value shows how many valid entries are currently in the Receive FIFO.
The following bit table shows the bit locations corresponding to the status and flag bits
within the SSP status register. All bits are read-only except ROR, which is read/write.
Writes to TNF, RNE, BSY, TFS, and RFS have no effect. The reset state of ROR is
unknown and must be initialized before enabling the SSP. Note that writes to reserved
bits are ignored and reads to those bits return zeros.
SSP Interrupt Test Register
Offset 0Ch: SSITR - SSP Interrupt Test Register Details
Writing ‘1’ to the corresponding bit position to the SSP Interrupt Test register generates
an interrupt strobe signal to the Interrupt Controller for test purposes.
SSITR functionality is available even when the SSP is disabled.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1616
August 2009
Order Number: 320066-003US