EP80579 Datasheet, PDF (1132/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.3
30.3.1
30.3.2
Route Control registers, located at 60–63h and 68–6Bh in Device 31, Function 0. One
or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not
required, the Route registers can be programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a platform to share a single line across the connector. When PIRQx# is routed to
specified IRQ line, software must change the corresponding ELCR1 or ELCR2 register to
level sensitive mode. The IICH internally inverts the PIRQx# line to send an active high
level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no
longer be used by an ISA (legacy) device. Internal sources of the PIRQs, including SCI
and TCO interrupts, cause the external PIRQ to be asserted. The IICH receives the
PIRQ input, like all of the other external sources, and routes it accordingly.
Advanced Interrupt Controller: APIC
In addition to the standard ISA (legacy)-compatible PIC described in the previous
chapter, the IICH also incorporates the APIC.
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal data path to the processor, and interrupts are
handled without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in the IICH supports a total of 40 interrupts (24
interrupts only, when ETR3.GPIO_IRQ_STRAP_STS is 0).
— When GPIO_IRQ_STRAP_STS field of Extended Test Mode Register3(ETR3) is 0,
MRE field in the APIC_VS register reports 17h (indicating 24 supported IRQs).
— When ETR3.GPIO_IRQ_STRAP_STS is 1 (Strap pulling “siu2_txd_ad18” to LOW
on the rising edge of PWROK), IO-APIC can support additional 16, dedicated,
GPIO driven IRQs (IRQ24-39). The function of IRQ capable GPIO pins are set to
IRQ mode by default if ETR3.GPIO_IRQ_STRAP_STS is 1, but can be changed
to GPIO mode for any or all of those pins by programming the GPIO_USE_SEL
registers. If the GPIO_USE_SEL register bits are configured to GPIO mode then
those GPIO pins can not generate IRQ interrupt to IO-APIC.
— Note: GPIO pins can not generate interrupt when ETR3.GPIO_IRQ_STRAP_STS
is 0.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.
PCI/PCI Express* Message-Based Interrupts
When external devices through PCI/PCI Express* wish to generate an interrupt, they
send the message defined in the PCI Express* Specification for generating INTA# -
INTD#. These are translated internal assertions/deassertions of INTA# - INTD#.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1132
August 2009
Order Number: 320066-003US