EP80579 Datasheet, PDF (855/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.1.2
Offset 04h: GHC – Global HBA Control Register
This register controls various global actions of the HBA.
Table 23-51. Offset 04h: GHC – Global HBA Control Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 04h
Offset End: 07h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30 : 02
01
00
Bit Acronym
Bit Description
Sticky
AE
Reserved
IE
HR
AHCI Enable (AE): When set, indicates that an AHCI
driver is loaded and communication to the HBA shall be
via AHCI mechanisms. This can be used by an HBA that
supports both legacy mechanisms (such as SFF-8038i)
and AHCI to know when the HBA is running under an AHCI
driver.
When set, software shall only talk to the HBA using AHCI.
The HBA will not have to allow command processing via
both AHCI and legacy mechanisms. When cleared,
software will only communicate with the HBA using legacy
mechanisms.
Software shall set this bit to ‘1’ before accessing other
AHCI registers.
Reserved
Interrupt Enable (IE): This global bit enables interrupts
from the HBA. When cleared (reset default), all interrupt
sources from all ports are disabled. When set, interrupts
are enabled.
HBA Reset (HR): When set by SW, this bit causes an
internal reset of the HBA. All state machines that relate to
data transfers and queuing will return to an idle condition,
and all ports will be re-initialized via COMRESET.
When the HBA has performed the reset action, it will reset
this bit to ‘0’. A software write of ‘0’ will have no effect. For
a description on which bits are reset when this bit is set,
see the AHCI specification.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RW
RO
RW
RWS
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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