EP80579 Datasheet, PDF (966/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.5.3
Note:
25.5.4
If not successful, and the error count has not been reached, leave the TD active. If
the error count has been reached, mark the TD inactive. Go to 12.
11. Write the link pointer from the current TD into the element pointer field of the QH
structure. If the Vf bit is set in the link pointer, go to 2.
12. Proceed to next entry.
Command Register, Status Register, and TD Status Bit
Interaction
Condition
USB Status Register Actions
CRC/Time Out Error Set USB Error Int bit¹, Clear HC Halted bit
Illegal PID, PID Error,
Maximum Length
(illegal)
Clear Run/Stop bit in command register
Set HC Process Error and HC Halted bits
Master/Target Abort
on memory accesses
Suspend Mode
Clear Run/Stop bit in command register
Set Host System Error and HC Halted bits
Clear Run/Stop bit in command register²
Set HC Halted bit
Resume Received
Suspend Mode = 1
Set Resume received bit
Run/Stop = 0
Clear Run/Stop bit in command register
Set HC Halted bit
Configuration Flag
Set
Set Configuration Flag in command register
HC Reset/Global
Reset
Clear Run/Stop and configuration Flag in
command register
Clear USB Int, USB Error Int, Resume
received, Host System Error, HC Process
Error, and HC Halted bits
IOC = 1 in TD Status Set USB Int bit
Stall
Set USB Error Int bit
Bit Stuff/Data Buffer
Error
Set USB Error Int bit¹
Short Packet Detect Set USB Int bit
Notes:
1.
Only If error counter counted down from 1 to 0.
2.
Suspend mode can be entered only when Run/Stop bit is 0.
TD Status Register Actions
Clear Active bit¹ and set Stall bit¹
Clear Active bit¹ and set Stall bit
Clear Active bit¹ and set Stall bit¹
Clear Active bit
If a NAK or STALL response is received from a SETUP transaction, a Time Out Error will
be reported. This will cause the Error counter to decrement and the CRC/Time-out
Error status bit to be set within the TD Control and Status Dword during write back. If
the Error counter changes from 1 to 0, the Active bit will be reset to 0 and Stalled bit to
1 as normal.
Transfer Queuing
Transfer Queues are used to implement a guaranteed data delivery stream to a USB
Endpoint. Transfer Queues are composed of two parts: a Queue Header (QH) and a
linked list. The linked list of TDs and QHs has an indeterminate length (0 to n).
The QH contains two link pointers and is organized as two contiguous DWords. The first
DWord is a horizontal pointer (Queue Head Link Pointer), used to link a single transfer
queue with either another transfer queue, or a TD (target data structure depends on Q
bit). If the T bit is set, this QH represents the last data structure in the current Frame.
The T bit informs the CMI that no further processing is required until the beginning of
the next frame. The second DWord is a vertical pointer (Queue Element Link Pointer) to
the first data structure (TD or QH) being managed by this QH. If the T bit is set, the
queue is empty. This pointer may reference a TD or another QH.
Intel^® EP80579 Integrated Processor Product Line Datasheet
966
August 2009
Order Number: 320066-003US