EP80579 Datasheet, PDF (258/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
9.4.2
9.4.3
9.4.4
individually designated to be coherent (snooped on the FSB) or non-coherent (not
snooped on the FSB), providing improvements in system performance and utilization
when cache coherence is managed by software rather than hardware.
Each of the four channels implements an independent set of configuration and status
registers, and is capable of fully independent operation. Each channel may operate in a
single block transfer mode, or a hardware traversed linked-list scatter/gather mode.
The internal EDMA controller only supports transfers between main memory locations,
and transfers from a main memory source to an I/O subsystem destination. The
internal EDMA controller supports neither transfers between I/O interfaces, nor
transfers from an I/O interface source to a main memory destination.
Integrated Memory Init/Test Engine
The IMCH provides hardware-managed ECC memory auto-initialization and testing of
all populated DRAM space under software control. Once internal configuration has been
updated to reflect the type and size of populated DIMM, the IMCH can traverse the
populated address space issuing line-sized writes of all zero data, thereby initializing all
locations with good ECC memory. This greatly speeds up the mandatory memory
initialization step and frees the CPU to pursue other machine initialization and
configuration tasks.
Additional features have been added to the initialization engine to support high-speed
population and verification of a programmable memory range with one of eight known
data patterns, random data, a walking data pattern, or an explicitly specified cache line
(data plus ECC). This function facilitates a limited high-speed memory test and
provides BIOS-accessible memory testing capability for potential use by management
code or by the operating system.
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
Coherent Memory Write Buffer
The IMCH includes an integrated coherent write buffer sized for 16 64-byte cache lines
(a total of 1 Kbyte of storage). This feature enables the IMCH to optimize memory read
latency, allowing reads to pass less critical writes en-route to the main memory store.
The write buffer includes a CAM structure to enforce ordering among conflicting
accesses to the same cache line, as well as to provide for read service from the write
cache. In the latter case, the access to the main memory store never occurs, which
both improves latency and conserves bandwidth on the memory interface.
The write buffer is capable of servicing processor read requests directly via a “hit” to
the internal location containing the data without initiation of any DDR subsystem
accesses. Inbound read requests such as PCI Express, i.e. not processor, which “hit”
the write buffer result in a flush of the target data, followed by retrieval via an external
read request.
Processor writes to shared non-coherent address space with the ASU result in a flush of
the current cacheline to main memory. ASU atomics will result in a DW write to the ASU
out of the write cache.
RASUM Features
The IMCH is designed to bring enterprise-level reliability, availability, serviceability,
usability, and manageability to the embedded platform. All internal SRAM memory
arrays are covered by parity. CMI’s PCI Express interface supports detection and
automatic recovery for all transient signaling errors. All IMCH internal configuration
Intel^® EP80579 Integrated Processor Product Line Datasheet
258
August 2009
Order Number: 320066-003US