EP80579 Datasheet, PDF (1195/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.6.2.2 Offset 01h: PV1R1 - Preload Value 1 Register 1
Table 33-27. Offset 01h: PV1R1 - Preload Value 1 Register 1
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 01h
Offset End: 01h
Size: 8 bit
Default: FFh
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Preload_Value_1 [15:8]: This register is used to hold
the bits 8 through 15 of the preload value 1 for the WDT
Timer. The Value in the Preload Register is automatically
transferred into the 35-bit down counter every time the
WDT enters the first stage.
PLOAD1_15_8 The value loaded into the preload register needs to be one
less than the intended period. This is because the timer
makes use of zero-based counting (i.e. zero is counted as
part of the decrement).
Refer to Section 33.6.3.2 for details on how to change the
value of this register.
Bit Reset
Value
FFh
Bit Access
RW
33.6.2.3 Offset 02h: PV1R2 - Preload Value 1 Register 2
Table 33-28. Offset 02h: PV1R2 - Preload Value 1 Register 2
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 0Fh
Power Well: Core
Bit Range
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
Preload_Value_1 [19:16]: This register is used to hold
the bits 16 through 19 of the preload value 1 for the WDT
Timer. The Value in the Preload Register is automatically
transferred into the 35-bit down counter every time the
WDT enters the first stage.
PLOAD_19_16 The value loaded into the preload register needs to be one
less than the intended period. This is because the timer
makes use of zero-based counting (i.e. zero is counted as
part of the decrement).
Refer to Section 33.6.3.2 for details on how to change the
value of this register.
Bit Reset
Value
0h
Fh
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1195