EP80579 Datasheet, PDF (1128/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.4
30.2.4.1
30.2.4.2
30.2.4.3
4. Upon observing the acknowledge cycle, it is converted into two cycles that the
internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge
pulse on the internal INTA# pin of the cascaded interrupt controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast internally by the master PIC to the
slave PIC. The slave controller determines if it must respond with an interrupt
vector during the second INTA# pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. If no interrupt request is present, the PIC will return vector 7 from
the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
Initialization Command Words (ICW)
Before operation can begin, each 8259 must be initialized. In the IICH, this is a four
byte sequence. The four initialization command words are referred to by their
acronyms: ICW1, ICW2, ICW3, and ICW4.
The base address for each 8259 initialization command word is a fixed location in the I/
O memory space: 20h for the master controller, and A0h for the slave controller.
ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, the IICH PIC expects three
more byte writes to 21h for the master controller or A1h for the slave controller to
complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
transition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special Mask Mode is cleared and Status Read is set to IRR.
ICW2
The second write in the sequence, ICW2, is programmed to provide bits [07:03] of the
interrupt vector that are released during an interrupt acknowledge. A different base is
selected for each interrupt controller.
ICW3
The third write in the sequence, ICW3, has a different meaning for each controller.
• For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the IICH, IRQ2 is used. Therefore, bit 2 of
ICW3 on the master controller is set to a 1, and the other bits are set to 0's.
• For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
Intel^® EP80579 Integrated Processor Product Line Datasheet
1128
August 2009
Order Number: 320066-003US