EP80579 Datasheet, PDF (1441/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.2
STATUS – Device Status Register
This register reports the status of the major operational modes for the device. This is a
read only register.
Table 37-26. STATUS: Device Status Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0008h
Offset End: 000Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0008h
Offset End: 000Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0008h
Offset End: 000Bh
Size: 32 bits
Default: 0000XXXXh
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
31 : 10
09 : 08
Rsvd
Reserved
Reserved
Reserved
Bit Description
Sticky
Bit Reset
Value
0h
X
Bit Access
RV
RO
Link Speed Setting: Reflects speed setting of the MAC.
07 : 06
05
04
03 : 02
01
00
SPEED
LINKMODE
TXOFF
Rsvd
RSVD
FD
In GMII/MII mode, these bits reflect the software
CTRL.SPEED setting
• 00 => 10 Mbps
• 01 => 100 Mbps
• 10 => 1000 Mbps
• 11 => 1000 Mbps
Mode. Based on CTRL_EXT. LINK_MODE.
0 = MAC is operating in GMII/MII mode
1 = Reserved
Transmission Off. This bit indicates the state of the
transmit function when symmetrical flow control has been
enabled and negotiated with the link partner.
0 = Symmetrical flow control is disabled, or transmission
is not paused.
1 = Symmetrical flow control is enabled, and the transmit
function is paused due to the reception of an XOFF
frame. It is cleared upon expiration of the pause timer
or the receipt of an XON frame.
Reserved
Reserved
Full Duplex. This bit reflects the MAC duplex
configuration. Normally, the duplex setting for the link, as
it should reflect the duplex configuration negotiated
between the PHY and link partner (copper link) or MAC and
link partner (fiber link).
0 = Half Duplex mode
1 = Full Duplex mode
X
RO
X
RO
X
RO
0h
RV
X
RO
X
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1441