EP80579 Datasheet, PDF (281/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.4
Main Memory Addressing
The “High Memory” and “Extended Memory” address regions are together called “Main
Memory.” Main memory is composed of address segments that refer to DDR SDRAM
system memory. Main memory addresses are mapped to DDR SDRAM channels,
devices, banks, rows, and columns in different ways depending upon the type of
memory being used and upon the density or organization of the memory. The process
for determining the device and channel IDs for addressed devices is as follows:
• The requested address is compared against the values of all eight DRB registers.
The number of the register whose programmed value is greater than the address
and whose previous register is less than the address is the output of the
comparison.
• The value of the DRB register “below” is subtracted from the address in order to
determine the offset into the group.
• The offset determines the manner in which the row, column, and bank address bits
are extracted from the address.
10.5
10.5.1
Note:
10.5.1.1
System Management Mode (SMM) Space
CMI supports the use of main memory as System Management RAM (SMM RAM)
enabling the use of System Management Mode. The IMCH supports three SMM options:
• Compatible SMRAM (C_SMRAM)
• High Segment (HSEG)
• Top of Memory Segment (TSEG)
System Management RAM space provides an access protected memory area that is
available for SMI handler code and data storage. This memory resource is normally
hidden from the Operating System so that the processor has immediate access to this
memory space upon entry to SMM (cannot be swapped-out).
SMM Addressing Ranges
IMCH provides three SMRAM options:
• Below 1 MByte option that supports compatible SMI handlers.
• Above 1 MByte option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
• Optional larger write-back cacheable T_SEG area from 128 Kbyte to 1 MByte in
size. The above 1 MByte solutions require changes to compatible SMRAM handler
code to properly execute above 1 MByte.
The first two options both map legal accesses to the same physical range of memory,
while the third defines an independent region of addresses.
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS
as available DRAM. This is a BIOS responsibility.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
281