EP80579 Datasheet, PDF (260/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
• Raw bit-rate on the data pins of 2.5 Gbit/s.
— Maximum theoretical realized bandwidth on the x8 PCI Express interface of 2
GByte/s in each direction simultaneously, for an aggregate of 4 GByte/s.
— Maximum theoretical realized bandwidth on the x4 PCI Express interface of 1
GByte/s in each direction simultaneously, for an aggregate of 2 GByte/s per
port.
— x8 sustainable data bandwidth is approximately 1.6 GByte/s in each direction
simultaneously
• Plesiochronous operation with automatic clock extraction and phase correction at
the receiver.
• Hierarchical PCI-compliant configuration mechanism for downstream devices
— Support for PCI Express memory-mapped enhanced configuration mechanism,
up to 4 Kbyte per device.
• 64 bit addressing support.
— 64 bit upstream addressing (full DAC support), limited to 32 bits internally to/
from system memory (external DDR).
— 32 bit downstream addressing support.
— Full 36 bit support for peer segment accesses.
Only 32-bit addresses can be snooped. Addresses larger than 32 bits will be truncated.
e.g. If a 36-bit address is snooped the upper 4 bits are ignored.
• Full-speed interface self-test and diagnostic (IBIST) functionality.
• Automatic discovery, negotiation, and training of PCI Express ports out of reset.
— Automatic detection of widest operational link; x8, x4 or x1.
• No support for Hot-plug via an external SMBus connected device.
• Run-time detection and recovery for loss of link synchronization.
• 32 bit CRC (cyclic redundancy checking) on all transaction layer packets with link-
level retry on error (recovery from transient errors without software-visible system
failure).
• 16 bit CRC on all link message information
• No support for the optional extended CRC (ECRC) mechanism
• Aggressive transceiver design to facilitate flexible system topologies
• Target BER of 10^-12 for physical signaling interface
• Support for peer segment destination write traffic (no peer-to-peer read traffic)
• Support for coherent and non-coherent transactions through EDMA to PEA to
external agent
• Support for both coherent and non-coherent traffic to memory within VC#0
— Non-coherent implies a combination of Snoop-Not-Required and Relaxed-
Ordering attributes
— Coherent traffic implies a combination of Snoop-Required and Strong-Ordering
attributes.
• Support for lane reversal at all native widths, and for reversed x4 training on any
x8 port
• Support for peer segment PCI interrupt forwarding to the IICH for boot from I/O
— Legacy mode support for level-sensitive interrupt emulation without IOxAPIC
support
Intel^® EP80579 Integrated Processor Product Line Datasheet
260
August 2009
Order Number: 320066-003US