EP80579 Datasheet, PDF (875/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.1.2.3 ATAPI
ATAPI DMA transfers are a combination of a PIO write command for the packet
command transfer, followed by a DMA command for the data transfer. See those
sections for a detailed explanation.
PIO data transfers are covered below.
23.5.1.2.4 Write to Device
Part I - Software Actions – Command Start
Software writes to the task file to set up the command, with the final write being to the
command register (1F7h, 177h).
Part II - Hardware Actions – Command Start
1. Upon seeing the command register written, hardware sends the register FIS to the
device, and awaits reception of either a PIO setup FIS or a device-to-host register
FIS.
2. Upon reception of the PIO setup FIS (since the command was a PIO command),
hardware updates the shadow block with the contents of the FIS and the current
status, and holds the E-Status in reserve. If the “I” bit was set, it generates an
interrupt.
Part III - Hardware / Software Actions – Data Transfer
Software writes to the data port as 16-bit quantities. Hardware assembles these writes
into its FIFO, and formulates a single DATA FIS to transmit the data. If software falls
behind the data transmission rate of the interface (very likely), hardware will insert
IDLE characters.
Part IV - Hardware Actions – Command Wrap-Up
After the last piece of data has been accepted by the device, hardware updates the
shadow block’s status register with the E-Status field.
Part V - Software Actions – Command Wrap-Up
1. Reading device status and BMIDE status
2. Complete request to OS
3. Error handling may occur, including device reset & DMA engine re-initialization.
23.5.1.2.5 Read from Device
The read ATA command is exactly the same as the write ATA command, except that in
Part III, hardware is receiving the DATA FIS and writing data to memory, instead of
fetching data from memory and sending a DATA FIS.
23.5.1.3
SW Assisted Queued DMA Transfer
In this mode of operation, SW supports queuing, the SATA device supports queuing,
but the SATA host controller does not. There are two general flows, one for a device
that does not support the DMA setup FIS, and one for a device that does support the
DMA setup FIS:
In both cases, SW is doing the work to determine the tag of the transfer. No special
hardware action is taken by the SATA host controller.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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