EP80579 Datasheet, PDF (981/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-5. Offset 04h: CMD - Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
01
00
Bit Acronym
Bit Description
MSE
IOSE
Memory Space Enable: This bit controls access to the
USB 2.0 Memory Space registers.
0 = Accesses to the USB 2.0 registers are disabled
1 = Accesses to the USB 2.0 registers are enabled.
The Base Address register for USB 2.0 must be
programmed before this bit is set.
I/O Space Enable: Reserved as '0'.
Sticky
Bit Reset
Value
0h
0h
Bit Access
RW
26.2.1.4
Note:
Offset 06h: DSR - Device Status Register
For the writable bits, software must write a one to clear bits that are set. Writing a zero
to the bit has no effect.
Table 26-6. Offset 06h: DSR - Device Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0290h
Power Well: Core
Bit Range
15
14
Bit Acronym
Bit Description
Sticky
DPE
SSE
Detected Parity Error:
0 = No SERR# detected.
1 = Set when a parity error is detected on the internal
interface to the USB host controller, regardless of the
setting of bit 6 or bit 8 in the Command register or
any other conditions.
Software clears this bit by writing a ‘1’ to this bit location.
Signaled System Error:
0 = No SERR# detected.
1 = This bit is set whenever it signals SERR# (internally).
The SERR_EN bit (bit 8 in the Command Register)
must be 1 for this bit to be set. The following
conditions can cause the generation of SERR#:
• A parity error is seen on address, command, or data
(if the data was targeting the EHC) on the internal
interface to the USBe host controller due to a parity
error on the system interface and bit 6 of the
Command register is set to 1.
• An EHC-initiated memory read results in a completion
packet with a status other than successful on the
system interface (if SERR on Aborts Enable is also set
to 1).
Software clears this bit by writing a ‘1’ to this bit location.
Bit Reset
Value
0h
0h
Bit Access
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
981