EP80579 Datasheet, PDF (1210/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-39. Logical Device 4 (Serial Port 1)
Logical Device Register
Address
Description
Enable
Default = 00h
I/O Base Address
Default = 00h
Primary Interrupt
Select
Default = 00h
Reserved
Default = 04h
Reserved
Default = 04h
Reserved
Default = 00h
30h
(RW)
60h
(RW)
61h
(Bits 7:3 RW
Bits 2:0 RO)
70h
(RW)
74h
Bits[7:1] Reserved, set to zero.
Bit[0]
1 =enable the logical device currently selected through the
Logical Device # register.
0 =Logical device currently selected is inactive
Registers 60h (MSB) and 61h (LSB) set the base address for the
device. Note: Decode is on 8 Byte boundaries
Comm Decode Ranges
3F8 - 3FF (COM 1)
2F8 - 2FF (COM 2)
220 - 227
228 - 22F
238 - 23F
2E8 - 2EF (COM 4)
338 - 33F
3E8 - 3EF (COM 3)
Bits[3:0] selects which interrupt level is used for the primary
Interrupt.
00= no interrupt selected
01= IRQ1
02= IRQ2
03= IRQ3
04= IRQ4
05= IRQ5
06= IRQ6
07= IRQ7
08= IRQ8
09= IRQ9
0A= IRQ10
0B= IRQ11
0C= IRQ12
0D= IRQ13
0E= IRQ14
0F= IRQ15
Bits[7:4] Reserved
Note: An Interrupt is activated by enabling this device (offset
30h), setting this register to a non-zero value and setting any
combination of bits 0-4 in the corresponding UART IER and the
occurrence of the corresponding UART event (i.e. Modem Status
Change, Receiver Line Error Condition, Transmit Data Request,
Receiver Data Available or Receiver Time Out) and setting the
OUT2 bit in the MCR.
Bit 7:0 - Reserved
Bit 7:0 - Reserved
75h
Bit 7:0 - Reserved
F0h
Intel^® EP80579 Integrated Processor Product Line Datasheet
1210
August 2009
Order Number: 320066-003US