EP80579 Datasheet, PDF (1657/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 41-27. Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
0040h at
Offset Start: 20h
Offset End: 0043h at
20h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
2: 2
1: 1
0: 0
Bit Acronym
Bit Description
Sticky
Channel Reset.
When a '1' is written to this bit, the channel is returned to
crst
the same default state as when a power-on reset occurs.
After writing a '1' to this bit to reset the logic, the
firmware must write a '0' to the bit to indicate the end of
the reset.
Timestamp All messages.
• When this bit is set, the locking of the time snapshot
registers is inhibited. Each message is timestamped at
the reception of a start of frame delimiter (SFD),
regardless of whether the message is a Sync or Delay
ta
Request message. The timestamp is captured by the
Snapshot register which is never locked and therefore
must be read before the next SFD is received.
• When this bit is cleared, the timestamp taken after
the SFD is frozen or locked when a valid Sync or Delay
Request message is detected, until the software
resets it.
Master Mode.
• When this bit is set, it indicates that this channel is a
time master on the network.
mm
• When cleared, this bit indicates that this channel is in
slave mode.
The default after reset is slave mode.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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