EP80579 Datasheet, PDF (1095/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.10.3
27.10.4
27.10.5
PWROK Signal
The PWROK input must go active based on the core supply voltages becoming valid.
PWROK must not go high until at least 99 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values.This is required to meet the 100 ms delay from valid power to
PLTRST# deassertion in the PCI Specification, Rev. 2.3.
1. Traditional designs have an active-low reset button electrically ANDed with the
PWROK signal from the power supply and the processors voltage regulator module.
If this is done with CMI, the PWROK_FLR bit will be set. CMI treats this internally as
if the RSMRST# signal had gone active. However, it is not treated as a full power
failure. If PWROK goes inactive and then active (but RSMRST# stays high), then
CMI will reboot (regardless of the state of the AFTERG3 bit). If the RSMRST# signal
also goes low before PWROK goes high, then this is a full power failure, and the
reboot policy is controlled by the AFTERG3 bit.
2. SYSRESET# is recommended for implementing the system reset button. This saves
the external logic that is needed when the PWROK input is used. Additionally it
allows for better handling of the SM-Bus and processor resets, and avoids
improperly reporting or power failures.
3. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by CMI.
4. In the case of true PWROK failure, PWROK will go low first before the VRMPWRGD.
5. If the PWROK input is used to implement the system reset button, CMI does not
provide any mechanism to limit the amount of time that the processor is held in
reset. The platform must externally guarantee that maximum reset assertion specs
are met.
CPUPWRGD Signal
This signal is connected to the processor and is derived from two inputs: VRMPWRGD
signal (from the processor’s VRM) AND’d with the PWROK signal that comes from the
system power supply.
Controlling Leakage and Power Consumption During Low-Power
States
To control leakage in the system, various signals will tri-state or go low during some
low-power states.
General principles (these are board-level guidelines and are NOT CMI behavioral
rules):
• All signals going to powered down planes (either internal or external) must be
either tri-states or driven low.
• Signals with pull-up resistors must not be low during low-power states. This is to
avoid the power consumed in the pull-up resistor.
• Buses must be halted (and held) in a known state to avoid a floating input (perhaps
to some other device). Floating inputs can cause extra power consumption.
Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes will be tri-stated or
driven low.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1095