EP80579 Datasheet, PDF (592/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-214.Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register (Sheet
2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 14Ch
Offset End: 14Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 14Ch
Offset End: 14Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
11 : 05
04
03 :00
Reserved
DLPEDM
Reserved
Reserved
Data Link Protocol Error Detect Mask. [STICKY]:
0 = Detect Data Link Protocol Error
1 = Disable Data Link Protocol Error detection
Reserved
Sticky
Bit Reset
Value
0000000b
Bit Access
Y
0b
RW
0000b
RO
16.4.1.76 Offset 150h: COREDMASK - Correctable Error Detect Mask Register
The Correctable Error Detect Mask register controls detection of the individual errors.
An error event that is masked in this register is not logged in the Correctable Error
Status register, and is never reported. There is one mask bit corresponding to every
implemented bit in the Correctable Error Status register. These bits are sticky through
reset.
Table 16-215.Offset 150h: COREDMASK - Correctable Error Detect Mask Register (Sheet 1
of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 150h
Offset End: 153h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 150h
Offset End: 153h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 13
12
11 : 09
08
07
Bit Acronym
Bit Description
Reserved
RTTEDM
Reserved
RNREDM
BDEDM
Reserved
Replay Timer Timeout Error Detect Mask. This bit is
sticky through system reset.
0 = Detect Replay Timer Timeout error.
1 = Disable Replay Timer timeout error detection.
Reserved
REPLAY_NUM Rollover Error Detect MaskThis bit is
sticky through system reset.
0 = Detect REPLAY_NUM rollover
1 = Disable REPLAY_NUM rollover detection.
Bad DLLP Error Detect MaskThis bit is sticky through
system reset.
0 = Detect Bad DLLP error.
1 = Disable Bad DLLP error detection.
Sticky
Y
Y
Y
Bit Reset
Value
00000h
0b
000b
0b
0b
Bit Access
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
592
August 2009
Order Number: 320066-003US