EP80579 Datasheet, PDF (983/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.5 Offset 08h: RID - Revision ID Register
Table 26-7. Offset 08h: RID - Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 08h
Offset End: 08h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
The value reported in this register depends on the value
written to the Revision ID in Device 31, Function 0. This
RID
register follows the ICH revision ID scheme as defined in
Section 19.2.1.4, “Offset 08h: RID - Revision ID Register”
on page 736.
Bit Reset
Value
Variable
Bit Access
RO
26.2.1.6 Offset 09h: PI - Programming Interface Register
Table 26-8. Offset 09h: PI - Programming Interface Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 09h
Offset End: 09h
Size: 8 bit
Default: 20h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
Program Interface Conforms: A value of 20h indicates that
PIC
this USB 2.0 Host Controller conforms to the EHCI
Specification.
Bit Reset
Value
20h
Bit Access
RO
26.2.1.7 Offset 0Ah: SCC - Sub Class Code Register
Table 26-9. Offset 0Ah: SCC - Sub Class Code Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 0Ah
Offset End: 0Ah
Size: 8 bit
Default: 03h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
SCC
A value of 03h indicates that this is a Universal Serial Bus
Host Controller.
Bit Reset
Value
03h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
983