EP80579 Datasheet, PDF (1126/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.10 ELCR2 - Slave Edge/Level Control Register
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Table 30-15. ELCR2 - Slave Edge/Level Control Register
Description:
View: IA F
Base Address: 0000h (IO)
Size: 8 bit
Default: 00
Bit Range
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
ECL15
ECL14
Reserved
ECL12
ECL11
ECL10
ECL9
Reserved
Edge Level Control IRQ15:
0 = Edge
1 = Level
Edge Level Control IRQ14:
0 = Edge
1 = Level
Reserved.
Edge Level Control IRQ12:
0 = Edge
1 = Level
Edge Level Control IRQ11:
0 = Edge
1 = Level
Edge Level Control IRQ10:
0 = Edge
1 = Level
Edge Level Control IRQ9:
0 = Edge
1 = Level
Reserved. Must be zero.
Offset Start: 4D1h
Offset End: 4D1h
Power Well: Core
Sticky
Bit Reset
Value
Bit Access
0h
RW
0h
RW
0h
0h
RW
0h
RW
0h
RW
0h
RW
0h
Intel^® EP80579 Integrated Processor Product Line Datasheet
1126
August 2009
Order Number: 320066-003US