EP80579 Datasheet, PDF (1300/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.10.1.17 Offset E0h: PMCS – Power Management Control and Status Register
Table 35-108.Offset E0h: PMCS: Power Management Control and Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: E0h
Offset End: E1h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15
14 : 13
12 : 09
08
07 : 04
03
02
01 : 00
PME_STATUS PME Status (sticky)
DATA_SCALE Data Scale
DATA_SEL Data Select
PME_EN PME Enable (sticky)
RV
Reserved
NSR
No Soft Reset
RV
Reserved
PS
Power State
Sticky
Bit Reset
Value
0h
00b
0000b
0b
0000b
0h
0h
00b
Bit Access
RO
RO
RO
RO
RO
RO
RO
RW
35.10.1.18 Offset E4h: SCID – Signal Target Capability ID Register
The Signal Target Capability record defines how the device targets it signals to IA
agents. It is an 9B vendor-specific capability record and includes the SCID, SCP, SBC,
STYP, SMIA, and SINT fields of the configuration header.
For more information on signaling by AIOC devices, see Section 35.4, “Interrupt
Handling for AIOC Devices” on page 1235.
Table 35-109.Offset E4h: SCID: Signal Target Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: E4h
Offset End: E4h
Size: 8 bit
Default: 09h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
SCID
Capability ID: PCI SIG assigned capability record ID
(09h, vendor specific)
Sticky
Bit Reset
Value
Bit Access
09h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1300
August 2009
Order Number: 320066-003US