EP80579 Datasheet, PDF (1470/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-46. ICR2: Error Interrupt Cause Read Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08E0h
Offset End: 08E3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08E0h
Offset End: 08E3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08E0h
Offset End: 08E3h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
21
20
19 : 00
Bit Acronym
Bit Description
Sticky
ERR_TXDS
ERR_RXDS
RSVD
DMA Transmit Descriptor 2-bit ECC Error. The DMA
Transmit Descriptor Buffer uses a single-bit correct/multi-
bit detect ECC parity algorithm to protect the SRAM it uses
for a data buffer. This bit indicates that a multi-bit error
has occurred on a read from that data buffer. No indication
of a single-bit error correction will be given by hardware.
Note: If this interrupt asserts, further GbE DMA Reads
and Writes are blocked until software issues a soft
reset to the GbE by writing the Device Control
Register (CTRL.RST).
DMA Receive Descriptor 2-bit ECC Error. The DMA Receive
Descriptor Buffer uses a single-bit correct/multi-bit detect
ECC parity algorithm to protect the SRAM it uses for a data
buffer. This bit indicates that a multi-bit error has occurred
on a read from that data buffer. No indication of a single-
bit error correction will be given by hardware.
Note: If this interrupt asserts, further GbE DMA Reads
and Writes are blocked until software issues a soft
reset to the GbE by writing the Device Control
Register (CTRL.RST).
Reserved
Bit Reset
Value
0h
0h
0h
Bit Access
RCWC
RCWC
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1470
August 2009
Order Number: 320066-003US