EP80579 Datasheet, PDF (1356/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Upon receipt of a packet for this device, hardware stores the packet data into the
indicated buffer and writes the length, packet checksum, status, errors, and status
fields. Length covers the data written to a receive buffer including CRC bytes (if any).
Software must read multiple descriptors to determine the complete length for packets
that span multiple receive buffers.
For standard 802.3 packets (non-VLAN) the Packet Checksum is by default computed
over the entire packet from the first byte of the DA through the last byte of the CRC,
including the Ethernet and IP headers. Software may modify the starting offset for the
packet checksum calculation, refer to Section 37.6.4.13, “RXCSUM – Receive
Checksum Control Register” for details. To verify the TCP checksum using the Packet
Checksum, software must adjust the Packet Checksum value to back out the bytes that
are not part of the true TCP Checksum.
Status information indicates whether the descriptor has been used and whether the
referenced buffer is the last one for the packet. Refer to Figure 37-7 for the layout of
the status field. Error status information is shown in Figure 37-8.
Figure 37-7. Receive Status (RDESC.Status) Layout
7
6
5
4
3
2
1
0
PIF
IPCS TCPCS Rsvd
VP
IXSM EOP
DD
PIF: Passed in-exact filter
IPCS: IPv4 Checksum Calculated on Packet
TCPCS: TCP Checksum Calculated on Packet
Rsvd: Reserved
VP: Packet is 802.1q (matched VET MMR)
IXSM: Ignore Checksum Indication
EOP: End of Packet
DD: Descriptor Done
Packets that exceed the receive buffer size span multiple receive buffers. EOP indicates
whether this is the last buffer for an incoming packet. DD indicates whether hardware
is done with the descriptor. When set along with EOP, the received packet is complete in
main memory. Software can determine buffer usage by setting the status byte to 0
before making the descriptor available to hardware, and checking it for non-zero
content at a later time. For multi-descriptor packets, packet status is provided in the
final descriptor of the packet (EOP set). If EOP is not set for a descriptor, only the
Address, Length, and DD bits are valid.
The VP field indicates whether the incoming packet's type matches VET (i.e., if the
packet is a VLAN (802.1q) type). It will be set if the packet type matches VET and
CTRL.VME is set. For a further description of 802.1q VLANs please see “802.1q VLAN
Support” on page 1400.
When the Ignore Checksum Indication bit is deasserted (IXSM = 0), the IPCS and
TCPCS bits indicate whether the hardware performed the IPv4 or TCP/UDP checksum(s)
on the received packet, respectively. Pass/Fail information regarding the checksum is
indicated in the status bits as described below for IPE & TCPE. When IXSM = 1,
software should ignore the IPCS and TCPCS bits.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1356
August 2009
Order Number: 320066-003US