EP80579 Datasheet, PDF (133/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
4.2.1
4.2.1.1
4.2.1.2
4.2.2
IA-32 core/Platform
The IA-32 core supports two inbound signaling mechanisms that the EP80579 can use
to accept signals from other agents: a legacy interrupt (INTx) and a message-signaled
interrupt (MSI). The INTx mechanism encodes an interrupt on one of four out-of-band
interrupt signals that drive interrupt controllers in the IA platform. The MSI mechanism
encodes an interrupt as an in-band 32-bit write to a memory-mapped location. When
the platform observes a write to an MSI location, it generates an interrupt to the CPU.
The operating system or system software specifies, in large part, the data value that
travels with an MSI; the device has limited ability to change or modify this value in the
PCI MSI model.
The IA platform also supports signaling for errors through events that the platform
eventually maps onto interrupts, such as SERR or SMI. Section 5.0, “Error Handling”
discusses these mechanisms in further detail. These mechanisms are not used in
functional inter-agent signaling.
MSI and INTx Signaling
The EP80579 supports both MSI and INTx mechanisms to interoperate with IA platform
system software since not all operating systems or devices support MSIs. The PCI
configuration header of each device indicates the capabilities of the device (i.e., if it can
generate an MSI, which pin it uses in INTx mode, etc.) and also allows system software
to specify the signaling mechanism the device should use when the device is capable of
both MSI and INTx signaling. Further, when signaling the IA platform, software must
tolerate “warts” of the IA signaling model such as spurious interrupts, etc.
For outbound signaling from the IA-32 core to other agents, the EP80579 relies on
memory writes to MMIO locations to transport signals or IA can issue an MMIO read to
a device CSR.
GPIO Signaling
The EP80579 provides the ability to configure a subset of its GPIO pins as interrupts.
GPIO pins 16-21, 23-25, 27, 28, 30, 31, 33, 34, and 40 can function in either an
interrupt mode or as a GPIO. Each of these GPIO pins can be connected to a single
input on the APIC when software configures the GPIO as an interrupt. These pins are
then available to external devices, such as a device attached to the Local Expansion
Bus, for use as signals. The EP80579 handles signals arriving through a GPIO interrupt
are handled like all other interrupts connected to the APIC. For additional information,
see the GPIO material in Section 22.0, “General Purpose I/O: Bus 0, Device 31,
Function 0”.
Other Agents
The remaining agents that are relevant to the EP80579 signaling model can only signal
in the outbound direction; that is, they only generate signals from the agent into
EP80579. These agents operate as follows:
• IMCH, IICH, and externally-attached PCI devices generate IA platform INTx or MSI
signals based on PCI device and platform configuration. PCI mechanisms such as
SERR can also support error reporting (see Section 5.0, “Error Handling”).
• Gigabit Ethernet MAC generates a side-band interrupt signal.
• CAN, SSP, and IEEE 1588 Interfaces generate side-band interrupt signals.
• Externally-attached Local Expansion Bus devices generate side-band interrupt
signals. These signals are not carried on the Local Expansion bus itself but rather
are presented to the IA-32 core through GPIO pins that the system configures to
generate signals.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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