EP80579 Datasheet, PDF (1156/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.2.1.2
Offset 010h: GEN_CONF - General Configuration Register
General Behavioral Rules:
• Software can access the various bytes in this register using 32-bit or 64-bit
accesses.
• 32-bit accesses can be done to offset 010h or 014h, but not to offsets 011h, 012h,
013h, 015h, 016h, or 017h.
• 64-bit accesses can only be done to 010h.
Table 32-3. Offset 010h: GEN_CONF - General Configuration Register
Description:
View: IA F
Base Address: HPTC
Offset Start: 010h
Offset End: 017h
Size: 64 bit
Default: 0000000000000000h
Power Well: Core
Bit Range
63 :02
01
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
Reserved Reserved:
LEG_RT_CNF
Legacy Replacement Route: If the ENABLE_CNF and
LEG_RT_CNF bits are set, then the interrupts are routed
as follows:
Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC
Timer 2-n is routed as per the routing in the timer n config
registers.
0 = If the LEG_RT_CNF bit is not set, the individual
routing bits for each of the timers are used.
1 = Legacy Rout: If the LEG_RT_CNF bit is set, the
individual routing bits for timers 0 and 1 (APIC or
FSB) have no impact.
000000000000
h
RO
0b
RW
Overall Enable:
0 = The main counter halts (does not increment) and no
interrupts are caused by any of these timers.
1 = Enable any of the timers to generate interrupts.
00
ENABLE_CNF ^{For level-triggered interrupts, if an interrupt is pending}
when the ENABLE_CNF bit is changed from 1 to 0, the
interrupt status indications (in the various Txx_INT_STS
bits) are not cleared. Software must write to the
Txx_INT_STS bits to clear the interrupts.
0b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1156
August 2009
Order Number: 320066-003US