EP80579 Datasheet, PDF (100/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-4. Glossary Table (Sheet 3 of 5)
Term
Definition
Full Duplex
Gb/s
GB/s
A connection or channel that allows data or messages to be transmitted in opposite directions
simultaneously.
Gigabits per second (10⁹ bits per second)
Gigabytes per second (10⁹ bytes per second)
Global visibility
An operation is said to be globally visible when all side-effects of the operation are visible to
every observer in the system. For example, a write to some resource (e.g., memory location,
control register, etc.) R achieves global visibility when a read of R by all other agents is
guaranteed to return the new value.
Gx States
Global system states (Gx states) apply to the entire system and are visible to the user.
• G3: Mechanical off - A computer state that is entered and left by a mechanical switch. It is
implied by the entry of this off state through a mechanical means that no electrical current
is running through the circuitry and that it can be worked on without damaging the
hardware or endangering service personnel.
• G2/S5: Soft Off - A computer state where the computer consumes a minimal amount of
power.
• G1: Sleeping - A computer state where the computer consumes a small amount of power,
user mode threads are not being executed, and the system “appears” to be off (from an
end user’s perspective, the display is off, and so on).
• G0: Working - A computer state where the system dispatches user mode (application)
threads and they execute. In this state, peripheral devices are having their power state
changed dynamically.
Half Duplex
A connection or channel that allows data or messages to be transmitted in either direction, but
not simultaneously.
Implicit Writeback
A snoop-initiated data transfer from the bus agent with the modified Cache Line to the memory
controller due to an access to that line.
Inbound
A transaction where the request destination is the processor-memory complex and is sourced
from I/O. The terms Inbound and Outbound refer to transactions as a whole and never to
Requests or Completions in isolation. (e.g., an Inbound Read generates Downstream data,
whereas an Inbound Write has Upstream data. Even more confusing, the Completion to an
Inbound Read travels Downstream.)
Industry Standard Architecture
A 16-bit bus architecture associated with the IBM AT motherboard designed to connect
motherboard circuitry to expansion card devices that is now considered Legacy.
Initiator
The source of requests. [IBA] An agent sending a request packet on 3GIO is referred to as the
Initiator for that Transaction. The Initiator may receive a completion for the Request. [3GIO]
ISA Regime
A special legacy mode to support ISA-based devices which have been integrated into the
chipset. It opens a dedicated channel from the peripheral device to the processor bus. While in
this mode, the legacy device is granted exclusive accesses to memory and the ability to use
Tenured Transactions.
Isochronous
A classification of transactions or a stream of transactions that require service within a fixed
time interval.
Lane
A set of differential signal pairs, one pair for transmission and one pair for reception. A by-N
Link is composed of N Lanes.
Layer
A level of abstraction commonly used in interface specifications as a tool to group elements
related to a basic function of the interface within a layer and to identify key interactions
between layers.
Legacy
Functional requirements handed down from previous chipsets, or PC compatibility
requirements from the past.
Link
The collection of two Ports and their interconnecting Lanes. A Link is a dual simplex
communications path between two components.
LPC Bus
Low Pin Count connection used to connect to the super I/O device.
Master
Mbyte/s
A device or logical entity that is capable of initiating transactions. A Master is any potential
Initiator.
Megabytes per second (10⁶ bytes per second)
Mem
Used as a qualifier for transactions that target memory space. (For example, a Mem read to I/
O.)
Intel^® EP80579 Integrated Processor Product Line Datasheet
100
August 2009
Order Number: 320066-003US