EP80579 Datasheet, PDF (1510/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.10 DC – Defer Count Register
This register counts defer events. A defer event occurs when the transmitter cannot
immediately send a packet due to the medium busy either because another device is
transmitting, half-duplex deferral events, or reception of XOFF frames. This register will
only increment if transmits are enabled.
Table 37-88. DC: Defer Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4030h
Offset End: 4033h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4030h
Offset End: 4033h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4030h
Offset End: 4033h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
DC
Number of defer events.
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.11 TNCRS – Transmit with No CRS Count Register
This register counts the number of successful packet transmission in which the CRS
signal from the PHY was not asserted within one slot time of start of transmission from
the MAC. Start of transmission is defined as the assertion of TX_EN to the PHY. The PHY
should assert CRS during every transmission. Failure to do so may indicate that the link
has failed, or the PHY has an incorrect link configuration. This register will only
increment if transmits are enabled and is only valid when the device is operating at half
duplex.
Table 37-89. TNCRS: Transmit with No CRS Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4034h
Offset End: 4037h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4034h
Offset End: 4037h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4034h
Offset End: 4037h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
TNCRS
Number of transmissions without a CRS assertion from the
PHY.
Bit Reset
Value
0h
Bit Access
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1510
August 2009
Order Number: 320066-003US