EP80579 Datasheet, PDF (33/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
33.5.1 UART Feature List .................................................................................1172
33.5.2 UART Operational Description .................................................................1173
33.5.2.1 Programmable Baud Rate Generator.................................................1174
33.5.3 UART Register Details ............................................................................1175
33.5.3.1 Offset 00h: RBR - Receive Buffer Register .........................................1176
33.5.3.2 Offset 00h: THR - Transmit Holding Register .....................................1176
33.5.3.3 Offset 01h: IER - Interrupt Enable Register .......................................1177
33.5.3.4 Offset 02h: IIR - Interrupt Identification Register ...............................1178
33.5.3.5 Offset 02h: FCR - FIFO Control Register ............................................1180
33.5.3.6 Offset 03h: LCR - Line Control Register.............................................1182
33.5.3.7 Offset 04h: MCR - Modem Control Register........................................1184
33.5.3.8 Offset 05h: LSR - Line Status Register ..............................................1185
33.5.3.9 Offset 06h: MSR - Modem Status Register.........................................1188
33.5.3.10 Offset 07h: SCR - Scratchpad Register .............................................1190
33.5.3.11 Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register
Low .............................................................................................1190
33.5.3.12 Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register
High.............................................................................................1190
33.5.4 FIFO Operation .....................................................................................1191
33.5.4.1 FIFO Interrupt Mode Operation ........................................................1191
33.5.4.2 FIFO Polled Mode Operation ............................................................1192
33.6 Logical Device 6: Watchdog Timer ....................................................................1192
33.6.1 Overview .............................................................................................1192
33.6.2 Watchdog Timer Register Details .............................................................1194
33.6.2.1 Offset 00h: PV1R0 - Preload Value 1 Register 0 .................................1194
33.6.2.2 Offset 01h: PV1R1 - Preload Value 1 Register 1 .................................1195
33.6.2.3 Offset 02h: PV1R2 - Preload Value 1 Register 2 .................................1195
33.6.2.4 Offset 04h: PV2R0 - Preload Value 2 Register 0 .................................1196
33.6.2.5 Offset 05h: PV2R1 - Preload Value 2 Register 1 .................................1196
33.6.2.6 Offset 06h: PV2R2 - Preload Value 2 Register 2 .................................1197
33.6.2.7 Offset 08h: GISR - General Interrupt Status Register..........................1197
33.6.2.8 Offset 0Ch: RR0 - Reload Register 0 .................................................1198
33.6.2.9 Offset 0Dh: RR1 - Reload Register 1.................................................1199
33.6.2.10 Offset 10h: WDTCR - WDT Configuration Register ..............................1199
33.6.2.11 Offset 18h: WDTLR - WDT Lock Register ...........................................1201
33.6.3 Theory Of Operation ..............................................................................1202
33.6.3.1 RTC Well and WDT_TOUT# Functionality ...........................................1202
33.6.3.2 Register Unlocking Sequence...........................................................1202
33.6.3.3 Reload Sequence ...........................................................................1202
33.6.3.4 Low Power State............................................................................1202
33.7 Serial IRQ .....................................................................................................1203
33.7.1 Timing Diagrams For SIW_SERIRQ Cycle..................................................1203
33.7.1.1 SIW_SERIRQ Cycle Control .............................................................1203
33.7.1.2 SIW_SERIRQ Data Frame ...............................................................1204
33.7.1.3 Stop Cycle Control .........................................................................1205
33.7.1.4 Latency ........................................................................................1205
33.7.1.5 EOI/ISR Read Latency ....................................................................1205
33.7.1.6 Reset and Initialization ...................................................................1205
33.8 Configuration .................................................................................................1206
33.8.1 Configuration Port Address ....................................................................1206
33.8.2 Primary Configuration Address Decoder....................................................1206
33.8.2.1 Entering the Configuration State ......................................................1206
33.8.2.2 Exiting the Configuration State ........................................................1206
33.8.2.3 Configuration Sequence ..................................................................1206
33.8.2.4 Configuration Mode ........................................................................1206
33.8.3 SIW Configuration Register Summary ......................................................1207
33.8.3.1 Global Control/Configuration Registers [00h - 2Fh].............................1208
33.8.3.2 Logical Device Configuration Registers [30h — FFh]............................1209
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
33