EP80579 Datasheet, PDF (69/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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23-24
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23-31
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23-61
23-62
23-63
23-64
23-65
23-66
23-67
with AHCI PI.................................................................................................... 826
Offset 24h: ABAR – AHCI Base Address Register................................................... 826
Offset 2Ch: SS - Sub System Identifiers Register.................................................. 827
Offset 34h: CAP – Capabilities Pointer Register..................................................... 827
Offset 3Ch: INTR - Interrupt Information Register ................................................ 828
Offset 40h: PTIM – Primary Timing Register ......................................................... 829
Offset 44h: D1TIM – Device 1 IDE Timing Register ............................................... 830
Offset 48h: SYNCC – Synchronous DMA Control Register ....................................... 831
Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register .................................... 832
Offset 54h: IIOC – IDE I/O Configuration Register .............................................. 833
Offset 70h: PID – PCI Power Management Capability ID Register ............................ 834
Offset 72h: PC – PCI Power Management Capabilities Register ............................... 834
Offset 74h: PMCS – PCI Power Management Control And Status Register ............... 835
Offset 80h: MID – Message Signaled Interrupt Identifiers Register .......................... 836
Offset 82h: MC – Message Signaled Interrupt Message Control Register................... 837
Offset 84h: MA – Message Signaled Interrupt Message Address Register.................. 838
Offset 88h: MD – Message Signaled Interrupt Message Data Register ...................... 838
Offset 90h: MAP – Port Mapping Register............................................................. 839
Offset 92h: PCS – Port Control and Status Register............................................... 840
Offset A8h: SATACR0 – Serial ATA Capability Register 0 ........................................ 841
Offset ACh: SATACR1 – Serial ATA Capability Register 1 ........................................ 841
Offset C0h: ATC – APM Trapping Control Register ................................................. 842
Offset C4h: ATS – ATM Trapping Status Register .................................................. 843
Offset D0h: SP – Scratch Pad Register ................................................................ 844
Offset E0h: BFCS – BIST FIS Control/Status Register ............................................ 844
Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register ........................................ 846
Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register ........................................ 846
Offset F8h: MANID – Manufacturing ID Register ................................................. 847
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through LBAR I/O BAR.......................................................................... 848
Offset 00h: PCMD – Primary Command Register ................................................. 848
Offset 02h: PSTS – Primary Status Register ....................................................... 849
Offset 04h: PDTP – Primary Descriptor Table Pointer Register ............................... 849
Offset 10h: INDEX – AHCI Index Register ............................................................ 850
Offset 14h: DATA – AHCI Data Register............................................................... 851
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through ABAR Memory BAR ................................................................... 852
Offset 00h: HCAP – HBA Capabilities Register ..................................................... 853
Offset 04h: GHC – Global HBA Control Register .................................................... 855
Offset 08h: IS – Interrupt Status Register .......................................................... 856
Offset 0Ch: PI – Ports Implemented Register ....................................................... 856
Offset 10h: VS – AHCI Version Register............................................................... 857
Offset A0h: SGPO -SPGIO Control Register .......................................................... 857
Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register .......... 858
Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register ......... 858
Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register ............................ 859
Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits Register ...... 859
Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register ............................... 860
Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register ............................... 861
Offset 118h: PxCMD[0-1] – Port [0-1] Command Register .................................... 863
Port Interface Registers for Ports[1:0] ................................................................ 866
Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register .............................. 866
Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register ..................................... 867
Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register ........................ 868
Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register ........................ 869
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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