EP80579 Datasheet, PDF (1395/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Note:
Note:
Note:
• Duplex (Full or Half)
• Flow Control Operation
PHY specific information required for establishing the link is also exchanged.
If flow control is enabled in the GbE, the settings for the desired flow control behavior
must be set by software in the PHY registers and Auto-Negotiation restarted. After
Auto-Negotiation is complete, the driver must read the PHY registers to determine the
resolved flow control behavior of the link and reflect these in the MAC register settings
(CTRL.TFCE and CTRL.RFCE).
There are two recommended methods for coordination between the PHY/PHY Auto-
Negotiation and the GbE. First, the PHY can be programmed to issue an MDINT to the
host CPU when the link changes. When the EP80579 receives the MDINT indicator via
an interrupt, the ISR routine will poll the PHY’s MDIO interface and programs the GbE
accordingly. Second, software may continuously poll the PHY’s configuration registers
through the MDIO interface and reprogram the GbE when the configuration changes
from the previous state.
MAC Speed Resolution
For proper link operation, both the MAC and PHY must be configured for the same
speed of link operation. The speed of the link may be determined and set by one of the
following methods:
• Hardware uses the default MAC speed of 1 Gbps and no software action is
necessary, or
• Software reads the PHY registers to determine the PHY's Auto-Negotiated speed
and configures the MAC by setting CTRL.FRCSPEED to 1 and CTRL.SPEED to the
proper speed value (refer to “CTRL – Device Control Register” on page 1438 for
details), or
• Software writes the non Auto-Negotiated PHY registers with the desired speed and
configures the MAC by to the same setting by programming CTRL.FRCSPEED to 1
and CTRL.SPEED to the proper speed value (refer to “CTRL – Device Control
Register” on page 1438 for details).
Forcing the MAC speed using CTRL.FRCSPD can yield non-functional links if the MAC
and PHY are not operating at the same speed/configuration.
The forcing of the speed settings by CTRL.SPEED may also be accomplished by setting
the CTRL_EXT.SPD_BYPS bit. This bit bypasses the MAC’s internal clock switching logic
and allows the driver complete control of when the speed setting takes place. The
CTRL.FRCSPD bit uses the MAC's internal clock switching logic, which does slightly
delay the affect of the speed change.
MAC Full/Half Duplex Resolution
The duplex configuration of the link is also resolved by the PHY during the Auto-
Negotiation process. For proper link operation, both the MAC and PHY must be also
configured for the same duplex configuration. The duplex configuration of the link may
be determined and set by one of the following methods:
• Hardware uses the default MAC speed of Full Duplex and no software action is
necessary (the PHY configuration must be KNOWN to be Full-Duplex for this
option), or
• Software reads the PHY registers to determine the PHY's Auto-Negotiated duplex
setting and configures the MAC by setting CTRL.FRCDPLX to 1 and CTRL.FD to the
proper value (refer to “CTRL – Device Control Register” on page 1438 for details),
or
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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