EP80579 Datasheet, PDF (1491/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5
37.6.5.1
Transmit Registers: Detailed Descriptions
TCTL – Transmit Control Register
This register controls packet transmission. Packet collision recovery, 64B data padding,
and software XOFF transmission are controlled here.
Table 37-67. TCTL: Transmit Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0400h
Offset End: 0403h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0400h
Offset End: 0403h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0400h
Offset End: 0403h
Size: 32 bits
Default: 00000008h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 25
24
23
22
21 : 12
Bit Acronym
Bit Description
Sticky
Rsvd
RTLC
PBE
SWXOFF
COLD
Reserved
Re-Transmit on Late Collision. This bit configures the
hardware to perform retransmission of packets when a late
collision is detected. Note that the collision window is
speed dependent: 64B for 10/100 Mbps and 512B for
1Gbps operation. If a late collision is detected when this bit
is clear, the transmit function assumes the packet is
successfully transmitted.
Note: This bit is ignored in full-duplex mode.
Packet Burst Enable. The EP80579’s GbE does not
support Packet Bursting for 1Gbps half-duplex transmit
operation. This bit must be set to 0.
Software XOFF Transmission. When set to a 1 the
device will schedule the transmission of an XOFF (PAUSE)
frame using the current value of the PAUSE timer. This bit
clears itself upon transmission of the XOFF frame.
Note: While 802.3x flow control is only defined during
full duplex operation, the sending of PAUSE frames
via the SWXOFF bit is not gated by the duplex
settings within the device. Software should not
write a 1 to this bit while the device is configured
for half duplex operation.
Collision Distance. Wire speeds of 1Gbps result in a very
short collision radius with traditional minimum packet
sizes. This bit specifies the minimum number of bytes in
the packet to satisfy the desired collision distance for
proper CSMA/CD operation. It is important to note that the
resulting packet has special characters appended to the
end, not regular data characters. Hardware strips special
characters for packets that go from 1 Gbps environments
to 100 Mbps environments.
Note: The hardware checks and pads to this value even
in full-duplex operation.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RV
RW
RV
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1491